ANNOUNCEMENT: ATPG for Verilog 
Author Message
 ANNOUNCEMENT: ATPG for Verilog

ATPG for Verilog-XL
-------------------

The University of Washington Design and Test Research Laboratory
(DTRL) has developed an experimental automatic test pattern generator
for the Verilog simulator.  It is now in alpha development and
undergoing testing at this time.

Abstract
--------

There currently exists many algorithms for test pattern generation.  
Generally, the input to these tools consists of a netlist, which is
not very user friendly or flexible to the designer.  As a result, it
became useful to apply these algorithms to work with a more logic
design-friendly environment, such as an HDL like Cadence's Verilog.
By having the test software closely coupled with the design tool, the
hope is that designers will be encouraged to consolidate the design
and test phases of their work and generate more testable designs.
Furthermore, by taking advantage of the Programming Language Interface
(PLI) to Verilog, the test tool can interact more intimately with the
simulator to ease the burden of test generation and fill a void
in the Veritool suite.

Capabilities
------------

The product is meant more as a proof of point than to be a production
quality piece of software, so the feature list is currently small.
The ATPG is a new system task ($atpg) that can generate test patterns
for stuck-at faults in gate-level descriptions in your design.  You
write your module description and then instantiate it in a test
fixture for it to be simulated under Verilog.  The following is an
example:

// $atpg example

module {*filter*}yweeny(m, l, a, b, c, e, f);
input a, b, c, e, f;
output m, l;

nand N1 (g, b, c),
     N3 (h, e, f),
     N2 (j, a, g),
     N4 (m, j, h);
not  N5 (l, j);

endmodule

module test_fixture;
reg a, b, c, e, f;
wire outm, outl, foutm, foutl;

{*filter*}yweeny good((outm, outl, a, b, c, e, f);
{*filter*}yweeny fault(foutm, foutl, a, b, c, e, f);

initial
    $atpg(good, fault);    // good and faulty modules

endmodule

Note that you instantiate your module twice so that you have a
good and faulty module.  Verilog does not support the traditional
5 or 9 fault values, so they are synthesized by comparing logic
values between the two modules after a fault is injected into the
faulty module.

$atpg will handle all non-sequential user primitives (and, or, nand,
nor, xor, xnor, buf, not) with any number of inputs.  Due to
limitations in PLI, behavi{*filter*}structures and assign statements are
not supported.  Block instantiations (hierarchy) are not supported as
of yet and neither is sequential logic (flip-flops, latches).

Algorithm
---------

The current algorithm implemented is a hybrid of Fujiwara's Fanout-
Oriented Test Pattern Generation (FAN) algorithm.

If you would like more information about this work, feel free to e-mail
me, and I can send you an electronic copy of my thesis when it's finished.

-Clint



Sun, 06 Apr 1997 02:49:02 GMT  
 ANNOUNCEMENT: ATPG for Verilog
|>
|> If you would like more information about this work, feel free to e-mail
|> me, and I can send you an electronic copy of my thesis when it's finished.
|>
|> -Clint

Can you send me more information about the tool ?

Thanks,

Luc

--
   _    /\
  ||  __||__            Luc Marent
  || | _||_ |          
 _||_||_||_||           IMEC vzw  VSDM
|_||_||_||_||           Kapeldreef 75, 3001 Leuven - Belgium
  ||_||_||_||_          Phone : 0032-016/281478
  |_ ___||_||_|
     ||    ||



Sun, 06 Apr 1997 17:43:18 GMT  
 
 [ 2 post ] 

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