*** Teamsters, Vegas, & DAC '96 *** 
Author Message
 *** Teamsters, Vegas, & DAC '96 ***


   /o o\  /  it's a FEATURE!"                                 (508) 429-4357
  (  >  )
   \ - /              The Fourth Annual ESNUG/DAC Awards:
   _] [_                 "Teamsters, Vegas & DAC '96"
                                   - or -
      "One Engineer's Review of DAC '96 in Las Vegas, NV, June 3-7, 1996"

                               by John Cooley

        Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
      Legal Disclaimer: "As always, anything said here is only opinion."

        [ Check out pg. 16 in this week's (June 17th) EE Times or
          "cooley.gif" at " http://www.*-*-*.com/ ;
          for the photo of the DAC freebies and their awards!  - John ]

Once I saw the AFL/CIO (the Teamsters) also having a conference in the same
hotel as DAC, I had this weird sense that Vegas more their town than ours.
These live-for-the-moment truckers drank like fish, would gamble away a
month's pay in an hour at a blackjack table, and could keep an army of those
"private {*filter*} dancers" busy in their hotel rooms until dawn.  In contrast,
my fellow more analytical engineers tended to drink lightly, only gambled a
little money at the best odds (which we carefully calculated), and were way
too afraid of AIDS to ever do anything more than look at a "private dancer."

While truckers impress each other with the inside scoop on Jimmy Hoffa, we
engineers "wow" each other by discussing undocumented Synopsys commands.
Truckers get belly laughs from telling offensive jokes about every race,
creed, gender and color; engineers get their kicks safely reading "Dilbert."
Clever engineers fret over which hot new start-up to join; clever truckers
try to figure out how to skim off of the Teamsters Retirement Fund.  (Even
marketing people see us as "different".  For conference freebies, truckers
got fun everyday guy stuff like 6-packs of beer, boxes of cereal, and
{*filter*}s.  We engineers only got cheap T-shirts, coffee mugs and puzzles...)

Although, I'm quite happy as an engineer, there's part of me now wondering:
"Is it too late to sign up for tractor trailer training school?"

Anyway, on with the 4th Annual ESNUG DAC Awards!

GREENPEACE AWARD: If EDA companies were living creatures, they'd be in one
healthy eco-system.  DAC grew 10 percent (to over 16,000 attendees) and the
exhibit floorspace itself increased 25 percent.  The exhibitor count jumped
from last year's 152 to this year's 164.  32 of last year's companies didn't
come back with their own booths this year -- only to be replaced by 37 new
companies.  Although i-Logix, Vista, and Harmonix moved on, most of the
missing 32 (like Attest, Exemplar, and Silerity) were gobbled up by larger
companies as part of the EDA food chain.  A few did simple name changes
like Intergraph becoming VeriBest; a few even mutated, like the RaviCad's
consulting becoming Virtual Chips, a PCI-IP company, -- but most of the
new 37 are companies with new ideas.

   "I don't know why they keep showing that stuff.  After three years
    they've still never had a single customer outside of IBM."

            - A user commenting on IBM EDA still showing BooleDozer
              and EinsTimer at this year's DAC.

   "Jesus!  We beg and grovel for a {*filter*}y $2 billion and these slimeballs
    just saunter on in with $7 billion!"

            - An EDA vendor commenting that the jewelry convention also in
              Vegas during DAC displayed $7 billion of merchandise.  (The
              EDA industry as a whole only nets about $2 billion per year.)

BIG CHICKEN AWARD: When Nanette Collins (who does PR for VHDL International)
asked me to attend DAC's first Workshop for Women in EDA (as an observer), a
little angel in my right ear said: "John, now you can share that Bill Clinton
part of you which strongly supports Equal Opportunity.  It'll be a teary-eyed
moment to celebrate our human diversity."  Then a little devil in my left ear
said: "Are you kidding!?!  Nanette wants {*filter*} for all that press about
sparsely attended VIUF's.  She knows the Rush Limbaugh side of you dislikes
Affirmative Action and is more than clever enough to make her fantasy
EE Times headline 'COOLEY KILLED BY ANGRY MOB OF EDA FEMINISTS' come true!"
(Self-preservation being a stronger instinct, I chickened out.  I later heard
101 women and two men attended: Bob Bellinger of EE Times and an unnamed
weasel/headhunter who kept asking everyone for their business cards.)

WORST FIRST IMPRESSIONS PARTY: Simplex Solutions took customers to see the
movie "Mission Impossible"; those who went were left stranded at a distant
theater with no taxi's.  Four AT&T engineers groused: "The final kicker was
when 5 Simplex people jumped in their car laughing and just drove away."

   "I guess the m{*filter*}is, don't entrust your life to a CAD vendor."

            - Eric McCaughrin of SGI, who took a defective Veritools water
              bottle on a 3 day camping trip in the Grand Canyon.

MOST UNORIGINAL "NEW" PRODUCT IDEA AT DAC: Cycle-based simulators.  At least
a dozen companies (SpeedSim, Frontline, Fintronic, Synopsys, Vantage,
Chronologic, Pendulum, Cadence, Cadence Alta, Synopsys, Mentor (rumored),
and CAE Plus) have or are working on one.  It's like the R&D staffs from
these companies all call the same psychic hotline for advice.

FIRST 3-D DEMO AT DAC: Mimicing the crowds of people in the 1950's who went
to watch 3-D movies, nearly 300 DAC attendees donned special polarizing
glasses to watch LogicVision's Built In Self Test (BIST) demo -- a DAC first.

VERILOG VS. VHDL (PART 2): This time it's analog.  The Verilog-A LRM was
approved at this DAC.  Cadence, Meta-Software and Apteq are alreay finalizing
their Verilog-A simulators.  (Nanette wasn't too happy informing me that the
VHDL-A LRM, which was supposed to be done by this DAC, was again delayed.)

   "I still stand by those words."

             - Cadence CEO Joe Costello about his IVC quote that VHDL "was a
               $400 million mistake."  (Ironically, Cadence also sells a VHDL
               simulator that has done quite well in the public benchmarks.)

IP WAS HOT: Companies like VLSI Libraries, 3Soft, Technical Data Freeway,
Virtual Chips, SAND, CAST and Synopsys were all getting attention from
customers wanting re-usable designs.  Not wanting to be left out, Xilinx
pushed its LogicCore program, Altera released its LPM to the public domain,
and Crosspoint touted its CoreBank program for third party designs.  (There
were even hot rumors that these companies were in the act of forming some
sort of "IP Alliance" at DAC.)  Some even saw Casacade as an IP company.

FUNCTIONAL VERIFICATION WAS HOTTER: Eagle Design, DS Diagonal Systems,
Chronology, Cadence Alta, NuThena, and even the tiny Levetate got special
consideration from engineers trying to verify designs.  But what most users
ranted about was the newbie InSpec.  While most companies in this category
(which was easily confused with HW/SW Co-design) pretty much offered waveform
viewers and a framework all wrapped up in a glitzy GUI, InSpec gave users
an automatic way to generate functional test vectors combined with a clever
graphical analysis tool that quickly points out coverage holes.  System
Science also offers a dialect of Verilog that makes test generation easier.

MOST IMPROVED COMPANY: ViewLogic.  They're no longer hemorrhaging employees
(in fact, they're growing), the legal battle with the old Chronologic staff
is *finally* over, and instead of giving out cheesy white T-shirts, this year
they gave out golfer's putters which tied with Altera's basketballs for
BEST DAC FREEBIE.  View/Silerity's datapath compiler can now use accurate
View/Quad MOTIVE timing plus interface to the third party Synopsys Design
Compiler.  View/Chronologic's VCS got ASIC sign-off status from Motorola,
LSI, Toshiba, and Lucent.  VCS Roadrunner is beefed up 5X to 10X plus it's
now integrated with the View/Quad MOTIVE static timing analyzer and the
View/Sunrise ATPG tools.  View/Chronologic's universally-executable-yet-
still-encrypted Verilog Model Compiler (VMC) is perfectly poised to take
advantage of the growing IP boom.  Good rebound, Viewlogic!

   "We started the user group and let it go.  Like many fledglings, it
    struggled for a bit and died.  I even think Sean Murphy was the
    Chairman the user's group at the time."

            - Viewlogic CEO Alain Hanover responding to Sean Murphy's
              asking about needing a user group to develop innovative tools.
              (Sean was never involved with Viewlogic's users group.)

   "To Alain Hanover, CEO of Viewlogic: What happened to the IC PowerTeam
    concept?  I don't hear about it anymore."

            - Daniel Payne, Mentor Graphics, who was the Viewlogic
              marketing manager for IC PowerTeam before joining Mentor.

"YES, YOU CAN TEACH AN OLD DOG NEW TRICKS" AWARD: Unlike Savantage's SavanSys,
which is more of an engineer's business analysis tool to juggle costs and a
system's physical implementation (by answering: "Would this work better as
5 small PCB's and a backplane or as 2 bigger PCB's with connectors?"),
Omniview's FIDELITY is truely a system-level synthesis tool.  An offshoot of
the Carnegie-Mellon "Micon" project, it works as an add-on to Mentor's
Design Architect and Viewpoint Editors.  The user enters in a block diagram
a very detailed, highly parameterized design which FIDELITY then breaks
down into specific commercial IC's.  It's a lot like schematic capture on
steroids and with a slightly higher IQ.

POWER! POWER! POWER!: The power freaks at this year's DAC got off on EPIC's
AMPS (a swapper that could optimize 30,000 transistor designs based on power,
delay and area), Simplex (for their circuit-level power analysis tools that
shows IC hot spots), Sente's Wat{*filter*}cher (an RTL-level pre-synthesis power
analysis tool), System Science's toolset, and Cadabra's LILA.  Synopsys Power
Compiler got some interest, but there were far too many companies with SPICE
level/mixed signal solutions to choose from at DAC: Agape, Anagram, Analogy,
Ansoft, Bell Labs, CAD-Migos, Cadence, Contec, Deutsch Research, Interactive
Image, Mentor, Meta-Soft, Microsim, OEA, Symetry, TMA, and VeriBest.

   "After 15 years in this business, you stop believing in physics."

            - Gary Smith of Dataquest, after a professor just explained how
              it's physically impossible to design at 0.18 microns.

   "We call them 'Cheech & Chong'."

             - An EDA competitor referring to Cooper & Chyan Technology.

MOST DRAMATIC NEW PRODUCT ANNOUNCEMENT: The Friday before DAC, Simon Perry,
Chief Editor of a British electronics publication phoned around in the EDA
community asking "What's Synopsys' big secret annoucement at DAC?"  On the
Free DAC Monday, Synopsys had a security guard standing next to a workstation
covered with black drapes and a big "?" sign.  There was an extra sign saying
"You can find out at 2:30 today."  At 2:30 they had over 200 people standing
around this draped workstation.  Moments before the big Synopsys 2:30 press
announcement, the Synopsys people even caught and kicked out Synplicity CEO
Alisa Yaffa while she protested: "Hey, this is a press announcement!!!  It's
public information!!!"  Turns out that Synopsys was annoucing FPGA Express,
a PC based FPGA synthesis tool that will directly compete with Synplicity.
(Oddly enough, I thought I heard Nanette whisper "YES!" when they said FPGA
Express had a built-in VHDL tutorial but no Verilog tutorial.)

   "Seventy percent of my sales are on the PC.  Seventy percent of my
    revenues are from UNIX."

            - ViewLogic CEO Alain Hanover two years ago justifying why
              he bought so many top of the line UNIX-based EDA companies.

   "Take a gamble on us!  SYNOPSYS"

            - The logo on the freebie pocket protectors Synopsys gave out
              at their DAC party four hours after announcing FPGA Express.

   "I'd be happy to provide them the catsup for the crow they're now eating."

            - Dan Ganousis of VeriBest, who pushed EDA on Windows NT for 3
              years, noticing how the big EDA companies are now jumping in.

MOST CURIOUS NEW COMPANY: TriQuest offers a finite state machine thingy
that does all sorts of bizarre optimizations, decompositions and
transmogrifications on RTL level state machine code.  Whoa!

"NICHE WITHIN A NICHE" AWARD: Promoting a funky sort of BIST, CrossCheck
sells the ability to make low power designs, fabbed only at Asian foundries,
fully testable.  Frequency Technology offers a sub-half-micron, interconnect
calculator that specializes in troublesome 3-D geometeries.  Two runners up:
Incases makes a 3-D radiation simulation tool for PCB design and K2 offers
"automated reticle synthesis and high speed viewing."

MOST LIKELY TO GET SUED: While other EDA vendors are trying to get
Synopsys to put their proprietary compiler directives and pragmas into the
public domain, ACEO Technology is already openly using them.

MOST APPROPRIATE FREEBIE: Cadence gave away free stopwatches so engineers
could time, in minutes, how long they still had a job once a Cadence
Spectrum Services salesman found their VP of Engineering.  You can even set
it to time in seconds once the Spectrum Technical Assessment Team arrives
at your site!  Cool!

   "OK, Spectrum Consulting may not be for everyone.  No one is making
    you use it.  I've never held a gun to anyone's head...   yet."

            - Cadence CEO Joe Costello responding to John Cooley's
              pointed questions about his consulting division.

BEST DAC PARTY: A tie between Quickturn and Mentor/Sun/HP.  Users loved the
Monday night party where Quickturn took everyone to see Penn & Teller's
comedy/magic show.  A lot of them enjoyed the quips Penn (the one who
speaks) took at engineers and Quickturn.  One such Penn quote: "Welcome to
Quickturn.  This is all mirrors, deception, misdirection and slight of
hand...   Oh, I'm speaking for Penn & Teller, not Quickturn right now."
Teller (the one who never speaks) even spoke to answer questions!  On Tuesday
night the hot party to crash was Mentor Graphic's 15th Anniversary (which was
also co-sponsored by Sun and HP.)  They rented the entire MGM Theme Park
where users got to see an acrobatic dualing pirate show, go on water rides
and simulated underground rides, see all sorts of roving musicians and odd
characters roaming the park (like clowns, giant mice, and Elvises) plus two
free drinks and dessert.  ("Beer and cake, yum!")  Everyone got a stuffed
dog doll and a nice Mentor/Sun knit shirt as freebies.

   "We had one influential Asian customer ask that we send both a male and
    a female {*filter*} to his hotel room.  Nobody knows what happened for
    those two hours -- but it cost my company $700."

            - An anonyous voicemail from someone claiming to be an EDA
              vendor responding to a survey question.

   "What's 'parasitic extraction' ?!  Getting your ex-wife off of alimony?"

            - Overheard by a PR agent immediately after a press briefing.

"WHEN HARRY MET SALLY" FAKING IT AWARD: Escalade.  Most of the ESDA vendors
competed in the "Great ESDA Shootout" at the last HP Design SuperCon.  It
had an impact on these companies.  Wally Rhines, CEO of Mentor, said his
System Architect is being changed to make it more useable because of what
happened in the Shootout.  After clearing up a reporting snafu that Speed
Electronics did, I resynthesized Speed's design using FSM Compiler two
days before DAC, getting results of 1.80 nsecs -- placing Speed up with the
hand coders in the shootout.  And Summit Design should get some sort of DAC
FREQUENT FLYER BONUS AWARD for how much mileage they got out of doing so well
in the Shootout.  The kicker was that although Escalade chickened out of
the ESDA Shootout, they apparently were telling customers on the DAC floor
some incredible synthesis numbers they got from doing this shootout!

MOST CONTENT-FREE (AND ANNOYING!) FLOOR SHOW: For the *second year* in a row,
both users and EDA vendors felt the HP floor show was the most content-free
in all of DAC.  "I got so bored I didn't even wait around to get whatever
freebie they were giving out." said on EDA user.  The EDA vendors (especially
any within a four booth radius) were especially pissed with HP because they
had a very loud simulated earthquake every 20 minutes that was very annoying.

CAN'T KEEP IT UP AWARD: Many were frustrated that DACnet was down for most of
DAC.  "This year it vasn't vorth hacking.  It vas down so much nobody could
use it.", said the Swiss president of RubiCAD, Michael Reinhardt, who hacked
DACnet last year to send junk e-mail to potential customers.

   "Is there a technical person in the house?"

            - John Cooley to a room filled with hundreds of engineers
              when the microphones went dead on the DAC/CEO panel.

   "It's also an early warning system.  If you're at work and you're
    seriously thinking of opening and eating it, it's time to go home."

            - Michael McClure of Chronology, which gave away humorously
              relabelled cans of SPAM winning the FUNNIEST FREEBIE AWARD.

MOST "OUT OF SYNC" DAC PARTY: The official DAC "Black & Blue" biker party
was kept quite true to theme.  They gave everyone black T-shirts with a
red flaming DAC logo, they had lots of good food, an open bar that kept
serving until about midnight, and a band that played very dance-able music.
(I even saw Nanette dancing with her husband while she was wearing her
"VHDL Uber Alles!" T-shirt.)   They even had a temporary tatoo parlor plus
vintage Harlies occassionally going through the room.  The only problem was
this theme had virtually *nothing* to do with Las Vegas -- but it would have
fit in *perfectly* with last year's DAC in San Francisco where various
subcultures there truely love leather, tatoos, and men on motorcycles!

INTERESTING ODDS & ENDS: Design Acceleration, Veritools, Simutest, and
InterHDL offered Verilog tools like waveform displays to source code "lint"
programs to an optimizer for VCD files to queueing tools to Verilog/VHDL
translators.  On the VHDL side, LEDA offers another set of tools including
a VHDL encypter and Intellx demo-ed a VHDL analyzer.  Chronology's
TimingDesigner did automated timing diagrams and analysis on RTL-level code.
Design Acceleration, Veda, and Simulation Technologies are all plugging
Verilog/VHDL code coverage tools.  The SysAdmin types liked Platform
Computing's LSF, a workstation load balancer which helped users schedule
EDA tool runs over networks, Runtime's VOV, a tool that graphs dependencies
between thousands of files in a project, and Spectra Logic's carousel that
juggles either 60 4mm DAT's or 40 8mm cassettes to automatically back-up
240 to 280 gigabytes of disk.

   "I dunno.  I thought it said 'VeriCow' the first time I read it."

            - A user reacting to Simulation Technologies sign
              announcing their "VeriCov" coverage tool.

   "Our simulators are so hot, they knocked him out!"

            - Dan Ganousis, VeriBest, whose DAC booth manager passed out from
              heat exhaustion 10 minutes before the DAC floor show started.

TESTING FOR THE TRUELY PICKY: Not to be confused with wishy-washy functional
testing, these companies focus on finding *all* the bugs in a design.  ATG
plugged INTELLECT, a killer partial scan technology that can handle gated
and derived clocks, asynch logic, FF's, latches, RAM's and ROM's.  Attest
and Simucad are in the fault simulation software business.  Synopsys,
Mentor/CheckLogic, Viewlogic/Sunrise and Syntest were all doing ATPG demos.
Intellitech, Syntest and LogicVision barked about BIST and BSDL.  And still
in the new paradigm department, Chrysalis displayed the industry's first
interactive formal verification tool: Design Explore.

   "Formal verification isn't a nice thing to have on a project; it's an
    absolute must have!"

             - Alex Silbey, Silicon Graphics on the DAC verification panel.

"OBJECTS IN MIRROR ARE CLOSER THAN THEY APPEAR" AWARD: Although many users
feel Quickturn has the current lead over IKOS, Zycad, Aptix, Mentor/Meta-
Systems, and Synopsys/Arkos in the special-hardware-for-hardware-designers
market (especially since some of these aren't even on the market yet!), some
are now openly noticing how the growing gate counts in FPGA's from Xilinx,
Altera and Lucent might unexpectedly be changing this landscape.

MOST SUICIDAL DAC FREEBIE: Interactive Image gave away 300 completely free,
unrestricted copies of their $600 Electronic Workbench ($180,000 in total).
Hasn't anyone told these guys EDA vendors come to DAC to *sell* tools?

   "By the turn of the century, you will have 5 devices on your body with
    their own IP addresses.  Where you put them is your own business..."

             - Netscape CEO Jim Clark in his DAC Keynote address.

   "Yea, a few of us out dropped out of the EDA business to get into
    the Internet business.  Less hype and more money."

            - Overheard from an ex-CrossCheck employee.

THE SHAPE OF THINGS TO COME: The most immediate response engineers give is
"higher levels of abstraction" so they talk about Synopsys's Behavi{*filter*}
Compiler and High Level Design System's RTL-level floor planner.  Others
speculate: "Because silicon is cheap, ASIC design is going to be replaced by
embedded controllers -- so we best start learning to use HW/SW co-design
tools like Mentor/Microtec's XRAY toolset or Hyperceptions's DSP-specific
RIDE tool.", while many of the hype driven EDA developers aren't thinking
specific tools as much as: "Hey, the Internet is hot! -- let's make JAVA
based EDA tools that we sell on Web pages!"  

BACK TO THE "REAL" WORLD: After 5 days in mercenary Las Vegas, I was quite
happy to get back home.  The lights and glitz are fun, but it's not reality.
After sleeping two days to recover, I knew I was back into my normal routine
when I had started writing an EE Times column about the attendance numbers
for the recent co-located IVC and VIUF conferences.  Apparently over 650
attended the pro-Verilog IVC while less than 225 attended the pro-VHDL VIUF.
(Nanette's going to scream {*filter*}y {*filter*}!)

                               - John Cooley
                                 part-time EDA industry gadfly
                                 full-time contract ASIC/FPGA designer

P.S. If you thought this review was on-the-money or out-to-lunch, please tell
me.  I love getting frank, honest feedback from fellow engineers.

P.P.S. In replying, *please* don't copy back this entire article; a 14,400
baud modem attached to a 386 on a sheep farm can handle only so much! :^)

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 4258 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Mon, 07 Dec 1998 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. MFPW'96/NZFPDC'96 Call for Participation

2. CFP: MFPW'96/NZFPDC'96

3. Call for Participation: LOPSTR'96/ILP'96

4. LONG: Object World Frankfurt '96 and Internet Forum Europe '96 Conference Programs

5. Cooley's Great-Gobs-Of-Guilt-6-Months-After-DAC'97 DAC Survey

6. Cooley's Great-Gobs-Of-Guilt-6-Months-After-DAC'97 DAC Survey

7. euroFORTH'96 announce & call for papers

8. Advanced Program & Registration For SNUG '96

9. '96 OVI & SNUG

10. Workshop DD&LP at JICSLP'96 - 2nd Call for Papers

 

 
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