RE : Verilog Textio using PLI ( Read.c) . 
Author Message
 RE : Verilog Textio using PLI ( Read.c) .

Quote:
>Hi !!
>I am a very confident user of VHDL. See my answers in comp.lang.vhdl.
>I need to write a testbench
>in Verilog for a received netlist.
>Are there similar packages in Verilog like the textio package in VHDL ?
>I want to read data in from a file and use this data as a simulation
>testbench.
>Any ideas ?
>Regards
>Braam Greyling

Hi !!

   I'm currently using the read.c file along with PLI , which I
downloaded from

    http://www.*-*-*.com/

This file has various functions with it that will

read stimulus files to apply patterns to the inputs of a model
read a file of expected values for comparison with your model
read a script of commands to drive a simulation
read either ASCII or binary files into Verilog regs and memories

I used it to read the parameter files and fill that data in my test
bench memories.
Example to illustatre the ease of using it

  The parameter file structure is somewhat as follows
    no_of_data_hex_items  10
    item1 234ab
    item2 cd68
     |
     |
     |
    item10 1234

  No_of_time_event  2
  Time_of_event_in_ns 1200
  time                1800

The values can be in hex, binary, time( decimals ). (Well I didn't try
for a real value input to verilog )
  Now this parameter file is read in verilog test bench and accordingly
actions are performed at that time.

 I compiled this read.c and used it with MODELSIM as well as Verilog XL
and found running well. On NC verilog it is not running ,but I'm trying
. If anybody used it sucessfully , let me know.

You can use this read.c file to solve your need.

Hope this helps

--------Ajit Madhekar

Sent via Deja.com http://www.*-*-*.com/
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Sat, 15 Dec 2001 03:00:00 GMT  
 
 [ 1 post ] 

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