Verilog vs. VHDL 
Author Message
 Verilog vs. VHDL

I have lots of war stories from the founding of Chronologic (June
1991). You wouldn't believe the number of "industry experts" who told
me that I was either wasting my time producing a Verilog simulator, or
that it might be an interesting short-term opportunity, but in 3 years
the world would be VHDL. It was literally everyone who makes a living
at prognosticating the EDA business.

Why is the design community more solidly Verilog-oriented than ever?
What happened (or didn't happen) to make these predictions wrong?
While people in this group generally look for techinical differences
in the languages, if you look at the business situation (that is,
money), it is clear that there is one winner in this "war", and that
is Verilog. Companies developing new products go where the money is,
and the money is overwhelmingly in the Verilog part of the market. The
last numbers (from Dataquest, no less) have Verilog products
outselling VHDL products by more than 2-1 (in revenue, not licenses),
and the real difference is almost certainly higher.

My own opinion of the fundamental reason for Verilog's staying power
is that Verilog had a very large head start in number of engineers who
knew Verilog before VHDL really got out of the blocks, and Verilog is
easier to learn than VHDL. Thus, the established designers already
knew Verilog, and had no reason to learn VHDL, and the new designers
could pick it up easier than they could pick up VHDL.

You can argue all you want about the technical merits of the two
languages, and the "understandability" of each. I know that I
personally learned Verilog in a very short period of time. Later, when
I decided that I really should learn VHDL in order to be able to
market my product against it, I found that learning VHDL really was
harder. I'm sure I've spent more effort trying to learn VHDL than I
did in the early days of my Verilog use, and I'm only barely literate
in VHDL. (Admittedly, I'm a little handicapped in that I never learned
Ada, but C wasn't my first (or even second or third) language,
either.)

When you couple this lower barrier to using Verilog with the fact that
there is really no good reason to switch from Verilog to VHDL (and
until VITAL there were good reasons to switch from VHDL to Verilog),
it is easy to see why the market didn't move the direction the pundits
believed it would.

John Sanguinetti



Fri, 30 Oct 1998 03:00:00 GMT  
 Verilog vs. VHDL

Quote:

> My own opinion of the fundamental reason for Verilog's staying power
> is that Verilog had a very large head start in number of engineers who
> knew Verilog before VHDL really got out of the blocks, and Verilog is
> easier to learn than VHDL. Thus, the established designers already
> knew Verilog, and had no reason to learn VHDL, and the new designers
> could pick it up easier than they could pick up VHDL.
....
>(Admittedly, I'm a little handicapped in that I never learned
> Ada, but C wasn't my first (or even second or third) language,
> either.)

I think you hit the nail on the head here - these days many if not
most  students learn C in school, very few learn Ada. Which means
that people have a leg up learning Verilog when the time comes

        Paul

----------------------------------------------------------------
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"I am Scamizdat" - aren't we all
"RUNDOWN DE FAUX BUTS" is a trade-service mark of Scientology
(and probably their plastic surgeons)



Fri, 30 Oct 1998 03:00:00 GMT  
 Verilog vs. VHDL

Once I got the books I learned verilog pretty fast.  Probably knowing
C helped.

But our bookstore stocks VHDL books, but Verilog was special order from
the publisher with a six-week delay.  

I have looked at some VHDL code, and it looks much harder to read for
similar functionality.  I write mostly structural verilog, though, maybe
it is different for behavi{*filter*}verilog.  

-- glen



Sat, 31 Oct 1998 03:00:00 GMT  
 
 [ 3 post ] 

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