verilog syntax question 
Author Message
 verilog syntax question

Hi,
    In the following code list, I understand something like
.SECS(CONNECT5)? What does the point mean? And what do the variables
within the parentheses mean?
Thanks!
Peng

module TIME_BLOCK ( SET_TIME, HRS, MINS, CLK, CONNECT6,
     CONNECT7,
     CONNECT8 );
input  SET_TIME, HRS, MINS, CLK;
output [3:0] CONNECT6;
output [5:0] CONNECT7;
output  CONNECT8;
    wire CONNECT3, CONNECT4, CONNECT5;
    TIME_STATE_MACHINE U1 ( .TIME_BUTTON(SET_TIME),
.HOURS_BUTTON(HRS),
        .MINUTES_BUTTON(MINS), .CLK(CLK), .SECS(CONNECT5),
.HOURS(CONNECT3),
        .MINS(CONNECT4) );
    TIME_COUNTER U2 ( .SECS(CONNECT5), .HOURS(CONNECT3),
.MINS(CONNECT4),
        .CLK(CLK), .HOURS_OUT(CONNECT6),
        .MINUTES_OUT(CONNECT7) ,
        .AM_PM_OUT(CONNECT8) );
endmodule



Tue, 03 Jan 2006 01:18:43 GMT  
 verilog syntax question
Hi Peng:

it's how you use a port from another module.

Let's say that we have a module like a buffer -

module BUF (A, Y)

to instantiate this in a file

PengsBuf  Buf (.A(PengsInput),
                         .B(PengsOutput));

this would assign PengsInput to the A port of the buffer, and
PengsOutput to the Y port of the buffer

Andrew

Quote:

>Hi,
>    In the following code list, I understand something like
>.SECS(CONNECT5)? What does the point mean? And what do the variables
>within the parentheses mean?
>Thanks!
>Peng

>module TIME_BLOCK ( SET_TIME, HRS, MINS, CLK, CONNECT6,
>     CONNECT7,
>     CONNECT8 );
>input  SET_TIME, HRS, MINS, CLK;
>output [3:0] CONNECT6;
>output [5:0] CONNECT7;
>output  CONNECT8;
>    wire CONNECT3, CONNECT4, CONNECT5;
>    TIME_STATE_MACHINE U1 ( .TIME_BUTTON(SET_TIME),
>.HOURS_BUTTON(HRS),
>        .MINUTES_BUTTON(MINS), .CLK(CLK), .SECS(CONNECT5),
>.HOURS(CONNECT3),
>        .MINS(CONNECT4) );
>    TIME_COUNTER U2 ( .SECS(CONNECT5), .HOURS(CONNECT3),
>.MINS(CONNECT4),
>        .CLK(CLK), .HOURS_OUT(CONNECT6),
>        .MINUTES_OUT(CONNECT7) ,
>        .AM_PM_OUT(CONNECT8) );
>endmodule



Tue, 03 Jan 2006 04:58:38 GMT  
 verilog syntax question

Quote:

> Hi,
>     In the following code list, I understand something like
> .SECS(CONNECT5)? What does the point mean? And what do the variables
> within the parentheses mean?

You might want to purchase a Verilog book!

Quote:
>     TIME_STATE_MACHINE U1 ( .TIME_BUTTON(SET_TIME),
> .HOURS_BUTTON(HRS),
>         .MINUTES_BUTTON(MINS), .CLK(CLK), .SECS(CONNECT5),
> .HOURS(CONNECT3),
>         .MINS(CONNECT4) );
>     TIME_COUNTER U2 ( .SECS(CONNECT5), .HOURS(CONNECT3),
> .MINS(CONNECT4),
>         .CLK(CLK), .HOURS_OUT(CONNECT6),
>         .MINUTES_OUT(CONNECT7) ,
>         .AM_PM_OUT(CONNECT8) );

You're instantiating a module called TIME_STATE_MACHINE.  This module
has a number of ports.

Verilog allows you to connect the module's ports to external signals
in two ways: by order, or by name.  Your module instantiation uses the
latter (which I prefer).

The connection:

     .TIME_BUTTON(SET_TIME)

connects a net that's *inside* the module, called TIME_BUTTON, to a
net in the instantiating module, called SET_TIME.

HTH,
a



Tue, 03 Jan 2006 07:09:30 GMT  
 
 [ 3 post ] 

 Relevant Pages 

1. VHDL to Verilog Syntax question

2. Verilog Syntax question

3. Verilog syntax question

4. Verilog syntax question

5. Verilog Syntax Question

6. VHDL to Verilog Syntax question

7. Verilog vector syntax question

8. Syntax Questions for a new language with somewhat Smalltalk-like syntax

9. block syntax/def syntax question/suggestion

10. Verilog ***** Verilog ***** Verilog ***** Verilog

11. Implementing letrec-syntax using only let-syntax and syntax-rules

12. Verilog Syntax Check

 

 
Powered by phpBB® Forum Software