Austin, TX or Cupertino, CA - Job Posting - Sr. Verification Engineer 
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 Austin, TX or Cupertino, CA - Job Posting - Sr. Verification Engineer

ASIC Verification Engineer

We are looking for candidates with an interest, background and
career focus in ASIC Design Verification to contribute to our
multi-million-gate ASIC projects. You'll need experience or
training in logic or system-level hardware design (Verilog-XL or
VHDL) and a strong software background (C, C++, Java or object-
oriented design).

Candidates will be responsible for developing complex object-
oriented software models and architectures which are used to
test our most complex ASIC designs in simulation. These projects
draw on and build strong hardware and software design knowledge.

Our group is responsible for design verification methodology for
all NSHD ASIC projects and multiple co-engineered projects with
other divisions within Compaq. We place no limits on what a
motivated contributor can do. Our group currently has Austin,TX
and Cupertino,CA based engineers, each with an average of 10
years industry experience. Our team has very low attrition, a
terrific 1st-pass silicon success record and no shortage of
interesting and challenging projects in the areas of fault-
tolerant clustering and switched-fabric I/O.

Junior-level positions are based in Austin, TX. Senior-level
positions are based in either Cupertino, CA or Austin, TX.

For more information, please contact:

Jeff Shaffer
Manager, ASIC Design Verification & Tools
Compaq Computer Corporation,  NonStop-TM Hardware Development,
Austin, TX

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Tue, 27 Aug 2002 03:00:00 GMT  
 
 [ 1 post ] 

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