Efficiency Question 
Author Message
 Efficiency Question

Hey!  I am writing a cache model for a superscalar design class and I am
attempting this in verilog (first time, I've seen it).  One section of
code is devoted to writing 1,2,3 or four bytes and I want to create soem
tight verilog.  The controlling signals are called EMICNTR and 00 = 1
byte, 01 = 2 bytes, etc.  Anyway, were I to write this in C I would
change the bounds of a bit select construct in a loop and loop once for
each byte.   That gave me an error of non-constant bit select.  I was
able to use the following work around, but I am unsatisfied with the
solution.  Were this to go to more than 4 bytes, my solution would
become REALLY ugly.  Any veriilog gurus have some suggestions ?

Email or post for others.

Domo arrigato gozaimasu!

Mark

`define SET 12:4                        // Set determines cache line
`define AWL 3:0                         // Address within cache line


        case (EMICNTR)
            2'b00: begin
                CacheRam[{Offset[`SET],Offset[`AWL]}] = LS_Data[7:0];
                end
            2'b01: begin
                CacheRam[{Offset[`SET],Offset[`AWL]}] = LS_Data[7:0];
                CacheRam[{Offset[`SET],Offset[`AWL+1]}] = LS_Data[15:8];
               end
            2'b10: begin
                CacheRam[{Offset[`SET],Offset[`AWL]}] = LS_Data[7:0];
                CacheRam[{Offset[`SET],Offset[`AWL+1]}] = LS_Data[15:8];
               CacheRam[{Offset[`SET],Offset[`AWL+2]}] = LS_Data[23:16];
               end
            2'b11: begin
                CacheRam[{Offset[`SET],Offset[`AWL]}] = LS_Data[7:0];
                CacheRam[{Offset[`SET],Offset[`AWL+1]}] = LS_Data[15:8];
               CacheRam[{Offset[`SET],Offset[`AWL+2]}] = LS_Data[23:16];
               CacheRam[{Offset[`SET],Offset[`AWL+3]}] = LS_Data[31:24];
               end
        endcase
        -> MarkBlockDirty;
end
--
  /\   Mark B. Lefevre
 _\/_  MCU Design    
/_/\_\ 3 Diamond Lane
       Durham, NC 27704



Thu, 03 Oct 1996 01:50:38 GMT  
 Efficiency Question
I've used a temporary memory before:

reg [7:0] tmp [0:3];
integer n;
...
{tmp[3],tmp[2],tmp[1],tmp[0]} = LS_Data[31:0];
n = 0;
repeat (EMICNTR + 1)
  begin
    CacheRam[{Offset[`SET],Offset[`AWL + n]}] = tmp[n];
    n = n + 1;
  end
...

NOTE: I'm not sure how this will impact performance - you have extra
assignments for the temporary memory elements, but the CacheRam
assignments are in the instruction cache of your machine if you do more
than one iteration.

                                                        John Williams



Sun, 06 Oct 1996 15:12:21 GMT  
 
 [ 2 post ] 

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