help: Using Synopsys's sldb and Cadence's verilog-XL? 
Author Message
 help: Using Synopsys's sldb and Cadence's verilog-XL?

Folks,

Help, could someone help me please?
I get some synopsys's library, actually DesignWare's component/module, in my
design after logic synthesis. However, the only verilog simulator is Cadence
verilog-XL, which is fine with the pre-synthesis simulation. But after the
logic synthesis, I don't know how to simulation/link the synopsys's library.
It is because the post-synthesis may change the delay too much, which is need
to verify.

Thank you very much
pun
--
Pun H. Shiu



Sun, 21 Oct 2001 03:00:00 GMT  
 help: Using Synopsys's sldb and Cadence's verilog-XL?
Quote:

> Help, could someone help me please?
> I get some synopsys's library, actually DesignWare's component/module, in my
> design after logic synthesis. However, the only verilog simulator is Cadence
> verilog-XL, which is fine with the pre-synthesis simulation. But after the
> logic synthesis, I don't know how to simulation/link the synopsys's library.
> It is because the post-synthesis may change the delay too much, which is need
> to verify.

  After synthesis, DesignWare component is mapped to cells of
technology library. So you don't need to link DesignWare library.
You should just have technology library in Verilog format.

  In Verilog-XL, you may make testbench like below...

`include "/technology_lib/vendor_db.v"
`include "/syn_db/my_syn_db.v"
...
...

-- ***************************************
-- Kyungjin Jang
-- DIT 2R, Daewoo Electronics CO., LTD.
-- ***************************************



Mon, 22 Oct 2001 03:00:00 GMT  
 
 [ 2 post ] 

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