Verilog equivalent of VHDL 'for...generate'? 
Author Message
 Verilog equivalent of VHDL 'for...generate'?

In VHDL it is possible to instantiate entities under control
of a for loop.  

I have heard that Verilog will soon have this feature too.

Can anyone comment?


Tommy Kelly


Sat, 20 Jul 1996 19:47:28 GMT  
 Verilog equivalent of VHDL 'for...generate'?
I have some familiarity with requests for Verilog "generate"
capability.  If anyone has more info or corrections, please post.

I believe that the latest Verilog Language Reference Manual from OVI
(ver 2.0?) has a specification for a Verilog "generate" statement.
However, I am not aware of any EDA vendor that has implemented this.
Also, if it hasn't been implemented, is sounds like it will be stripped
out of the Verilog version submitted to the IEEE.

I wish this were available.  If it were, you could do slick
configurable models of memories, etc.  We can't do this now because
Verilog-XL requires primitives to be instantiated for each I/O port to
support delay annotation.


Sat, 03 Aug 1996 07:13:47 GMT  
 [ 2 post ] 

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