VHDL vs Verilog 
Author Message
 VHDL vs Verilog

Which is the preferred language through the ASIC design flow?  Is one
language more widely supported than the other?  Is one language inherently
"better" than the other?

If this is a redundant issue, where can I find more info on this topic?

Thanks

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Tue, 02 May 2000 03:00:00 GMT  
 VHDL vs Verilog

I think the best way to determine which HDL is better is
to simply look where the $ for simulation licenses are
going...

EE Times (Oct 27, 1997 pg. 134) states that VHDL simulation
revenue FELL from $14.2 million in 1995 to $12.4 million
in 1997. Verilog simulation revenues GREW from $15.8 million
to $29.7 million in the same time period.

Chuck Shinn
Hewlett Packard Int Ckt Bus Div, Boise, Idaho



Tue, 02 May 2000 03:00:00 GMT  
 VHDL vs Verilog

This could start and annoyingly long thread/flame war.  Let me say as
having used both, that in general they do the same thing, but verilog is
MUCH easier to learn.  Unless you are going to need user defined types
or records as data types, there is little use for VHDL.  On the
otherhand, there are a better state machine styles possible in VHDL
(using a userdefined type for the states), and using record types to
describe "packets" in datacommunications systems is quite handy.

I would sum it up as, if you think everything is just a bit or
collection of bits, then Verilog is fine, If you need some of that other
stuff, then think about VHDL.  Again, the learning Curve for Verilgo is
MUCH shorter.

Quote:

> Which is the preferred language through the ASIC design flow?  Is one
> language more widely supported than the other?  Is one language inherently
> "better" than the other?

> If this is a redundant issue, where can I find more info on this topic?

> Thanks

> --
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>                                         /   / \  / / / / /__ /  \/ /___  /
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  Author "Verilog Quickstart" ISBN 0-7923-9927-7
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Tue, 02 May 2000 03:00:00 GMT  
 VHDL vs Verilog

FWIW:
    The lecturer at the last VHDL seminar I went to said that
    VHDL was better suited for FPGA's, and Verilog was better
    at the "full custom" stuff.

Gary.

: Which is the preferred language through the ASIC design flow?  Is one
: language more widely supported than the other?  Is one language inherently
: "better" than the other?

: If this is a redundant issue, where can I find more info on this topic?

: Thanks

: --
: -------------------------------------------------------------------------------
: jbarz                                     __  __     ____  ___       ___ ____

:                                         /   / \  / / / / /__ /  \/ /___  /
: -------------------------------------------------------------------------------



Wed, 03 May 2000 03:00:00 GMT  
 VHDL vs Verilog


Quote:
> Which is the preferred language through the ASIC design flow?
> Is one language more widely supported than the other?  Is one
> language inherently "better" than the other?

Firsly, the tools (Synopsys etc.) support both languages
well so that is not an issue.

In terms of language design, Verilog is pretty much a hack
compared to VHDL; however, it's enough easier to use that
generally labor costs will be somewhat lower in a big project if
you use Verilog.

VHDL might have the edge for very large, multi-person,
multi-product, multi-year projects in which the greater
regularity makes things easier to organize, and the
added training time of effectively learning a more complex
language is amortized over a greater cost base.

If you're only designing one ASIC, other things being
equal I'd use Verilog.

Steve



Wed, 03 May 2000 03:00:00 GMT  
 VHDL vs Verilog

Hi, everyone,

I am looking for a VHDL to verilog convertor, any suggestions?


Thanks in advance!

-claudia  



Fri, 05 May 2000 03:00:00 GMT  
 VHDL vs Verilog


Quote:

>Hi, everyone,

>I am looking for a VHDL to verilog convertor, any suggestions?


>Thanks in advance!

>-claudia  

Try interHDL, it is the most complete of the bunch (even if I am

www.interhdl.com, ftp.interhdl.com

Eli

--
Eli Sternheim
interHDL, Inc.
4984 El Camino Real, Suite 210
Los Altos, CA. 94022-1433
phone: 415-428-4200
fax:   415-428-4201



Sat, 06 May 2000 03:00:00 GMT  
 VHDL vs Verilog


Quote:
> Hi, everyone,

> I am looking for a VHDL to verilog convertor, any suggestions?


> Thanks in advance!

> -claudia  

Commercially such tools are available from

    1.Alternate System Concepts, Inc
      http://www.ascinc.com/products/listing.html
    2.interHDL
      http://www.interHDL.com/evaluation/translators.html
    3.X-Tek Corporation
      http://www.x-tekcorp.com/prod01.htm

This information along with other stuff is available at
Verilog FAQ
http://www.comit.com/~rajesh/verilog/faq/alt_FAQ.html

Visit my Verilog Page http://www.comit.com/~rajesh/verilog

Rajesh

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Sat, 06 May 2000 03:00:00 GMT  
 VHDL vs Verilog

|>
|> FWIW:
|>     The lecturer at the last VHDL seminar I went to said that
|>     VHDL was better suited for FPGA's, and Verilog was better
|>     at the "full custom" stuff.
|>

        That is so dependent on the synthesis tools that I don't
believe that generalization is possible at all.

|> Gary.
|>

|> : Which is the preferred language through the ASIC design flow?  Is one
|> : language more widely supported than the other?  Is one language inherently
|> : "better" than the other?
|>
|> : If this is a redundant issue, where can I find more info on this topic?
|>
|> : Thanks
|>
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Sun, 07 May 2000 03:00:00 GMT  
 VHDL vs Verilog

Joe,

In the Silicon Valley Verilog is King.  As a hardware description
language Verilog is just so much easier to describe digital circuits.
VHDL does have some nice features such as multi-dimensional arrays
and record structures, but your inquiry was for the ASIC design flow.
I just saw an article in the EE times about a month ago stating that
Verilog is far out selling VHDL.  The FPGA tools did have more support
for VHDL, but that has changed where most now support Verilog.

Here has been my experience:

1) If a designer has used Verilog first, he will hate VHDL.
2) If a designer has used VHDL first, they will complain about Verilog
   being deficient by not allowing enumerated types or records or
   something.  However, once that designer then goes back to VHDL after
   using Verilog and recalls how much extra overhead is required....
   suddenly the bad-mouthing of Verilog comes to halt.

As a general description: VHDL is based on ADA syntax and Verilog is
   based on C syntax.  This alone should make any sane individual
   choose Verilog

Al

Quote:

> Which is the preferred language through the ASIC design flow?  Is one
> language more widely supported than the other?  Is one language inherently
> "better" than the other?

> If this is a redundant issue, where can I find more info on this topic?

> Thanks

> --
> -------------------------------------------------------------------------------
> jbarz                                     __  __     ____  ___       ___ ____

>                                         /   / \  / / / / /__ /  \/ /___  /
> -------------------------------------------------------------------------------



Mon, 08 May 2000 03:00:00 GMT  
 VHDL vs Verilog



Quote:

>Your conclusion is wrong or I'm insane. I'll let it check over
>the weekend. But seems to me that large critical software projects
>are often written in ADA. Think f.i. of Airbus or Ariane software.
>The reason is of course that it must be really _reliable_ and
>_maintainable_ .

Without wanting to jump into trench warefare over VHDL and Verilog (I
work with both, but the bulk of my work is in C), there were probably
better examples than Ariane that you could have chosen. ;-)
--
/*  _  */main(int k,char**n){char*i=k&1?"+L*;99,RU[,RUo+BeKAA+BECACJ+CAACA"
/* / ` */"CD+LBCACJ*":1[n],j,l=!k,m;do for(m=*i-48,j=l?m/k:m%k;m>>7?k=1<<m+
/* |   */8,!l&&puts(&l)**&l:j--;printf("  \0_/"+l));while((l^=3)||l[++i]);}
/* \_,hris Brown -- All opinions expressed are probably wrong. */


Tue, 09 May 2000 03:00:00 GMT  
 VHDL vs Verilog



Quote:
> Joe,

> In the Silicon Valley Verilog is King.  As a hardware description
> language Verilog is just so much easier to describe digital circuits.
> VHDL does have some nice features such as multi-dimensional arrays
> and record structures, but your inquiry was for the ASIC design flow.
> I just saw an article in the EE times about a month ago stating that
> Verilog is far out selling VHDL.  The FPGA tools did have more support
> for VHDL, but that has changed where most now support Verilog.

> Here has been my experience:

> 1) If a designer has used Verilog first, he will hate VHDL.
> 2) If a designer has used VHDL first, they will complain about Verilog
>    being deficient by not allowing enumerated types or records or
>    something.  However, once that designer then goes back to VHDL after
>    using Verilog and recalls how much extra overhead is required....
>    suddenly the bad-mouthing of Verilog comes to halt.

I fit into your 1) catagory.  I really didn't like VHDL after using
Verilog, but after using VHDL for a while now, I don't think its as bad as
when I first started with it.  Maybe I just got numb to it.  There are
still a few things that VHDL could benefit from if it were more like
Verilog.  VHDL 93 helps with some of them, but Synopsys still does not
support 93.

--
Rich Iachetta
IBM Corporation



Tue, 09 May 2000 03:00:00 GMT  
 VHDL vs Verilog

I usually frain from posting to volatile message thread like
VHDL vs. Verilog in this group or {*filter*} Multilation (Circumcision)
in misc.kids but what the heck.

My personal opionion:

VHDL = More typing = longer time to finish = no dinner = bad

Verilog = Less typing = shorter time to finish = dinner at home = good

------------------------------------------------------
Steve Holmes                                          

http://www.*-*-*.com/ ~sholmes



Tue, 09 May 2000 03:00:00 GMT  
 
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