Rising_Edge/Falling_Edge Functions 
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 Rising_Edge/Falling_Edge Functions

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> > > Has anyone run into this problem. Does anyone have a "set"
> > > script (or something like that) that will allow me to
> > > continue using  Rising_Edge(clk) and Falling_Edge(clk)
> > > functions with Synopsys' tools?  Thank-you in advance.

> This has always annoyed me. Other synthesis tools do support
> RISING_EDGE (exemplar for one) which IMHO is just a whole lot
> more intuitive than clk'event AND clk='1'... Unfortunately I
> can't use it because god...I mean... Synopsys doesn't...

> I think we should put more pressure on synopsys to support this
> VERY SIMPLE feature of the 1164 standard...

> --

> VAutomation Inc.       Synthesizable VHDL and Verilog Cores
> 20 Trafalgar Sq. #443   http://www.*-*-*.com/
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Fri, 27 Aug 1999 03:00:00 GMT  
 Rising_Edge/Falling_Edge Functions

Unfortunately, the VHDL parser in Synopsys can't handle a function
call to detect a rising ege or falling edge inference. It must see:

   X'EVENT and X='0'

The only way I can see for you to be able to use the functions rising_edge() or
falling_edge() is to pre-process the code before reading into synopsys.

In the synopsys script you could have:

    sh cat FILE | perl -pe 's/rising_edge\(\s*(\w+)\s*\)/$1\047EVENT and $1=\0471\047/' > NEW_FILE
    read -for vhdl NEW_FILE

For non perl hackers, the above line probably looks grim. But it does work. The \047
part of the substitution represents '. \047 is needed because otherwise perl thinks
that ' is string delimiter and gets a bit confused.

So \0471\047 is really '1', but I guess this is all very confusing for non-perl
hackers.

Andrew

: > Has anyone run into this problem. Does anyone have a "set"
: > script (or something like that) that will allow me to
: > continue using  Rising_Edge(clk) and Falling_Edge(clk)
: > functions with Synopsys' tools?  Thank-you in advance.

: Although I'm not very familiar with Synopsys, you could use a function
: like this (off the cuff, after a few glasses of wine at home, so expect
: some error messages):

: FUNCTION Falling_edge(signal clock : std_ulogic) : BOOLENA
: BEGIN
:   IF (Clock'EVENT and Clock = '0') then
:     return TRUE
:   ELSE
:     return FALSE
:   END IF;
: END;

: Rising_edge should be trivial. If you define these in a package which
: you include you should be fine.

: Regards,

: Ben Twijnstra



Mon, 30 Aug 1999 03:00:00 GMT  
 
 [ 2 post ] 

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