code reuse 
Author Message
 code reuse

My group is being tasked this year as our IR&D project to incorporate
code reuse into our ASIC design process.  Is this feasible?  Are
there tools or programs that can assist with code reuse?  Can code
reuse truly improve schedules?  Can code really be reused?  What are
the drawbacks to code reuse?  Does anyone have any experiences (war
stories) regarding code reuse?

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Sat, 05 Oct 1996 22:00:06 GMT  
 code reuse
I wish there was an easy answer for that question, because it is a good
question. The impression I get from a lot of managers is that they expect
code to be reused in the form of libraries. Whether or not you can create
libraries that can be reused depends alot on how fast you change technologies.
I see no real solution to the basic problem of "bottom-up" reuse, that is,
technology changes too fast to make reusable libraries feasible. My opinion
is that you spend a lot of time designing and documenting the libraries, and
then next year you have a different technology.

I think the concept of reuse has been misapplied. Code reuse is a "top down"
strategy. A programming language like C++ incorporates a hierarchical class
structure, where the top most classes are likely to reused. Verilog does not
really support that kind of object oriented paradigm. In the meantime, my
personal opinion is that "reuse" is a popular buzzword that won't amount to
a whole lot.

I think the critical question becomes, will Verilog evolve into a language
that supports a top down code reuse paradigm? I don't think libraries are the
answer. Libraries are very transient. I think the answer lies in how Verilog
could support object oriented code. The higher level a design is, the more
likely it is to persist as part of the next design. The technology underneath
will be swept away. The abstraction is more permanent than the reality.

I just knew I'd be able to fit Plato in here if I waited long enough . . .

                                                John Williams



Tue, 08 Oct 1996 15:09:17 GMT  
 code reuse

+-----< John Williams >
|?[...] The impression I get from a lot of managers is that they expect
|?code to be reused in the form of libraries.
...
|?I think the concept of reuse has been misapplied. Code reuse is a "top down"
|?strategy.
...
|?The higher level a design is, the more
|?likely it is to persist as part of the next design. The technology underneath
|?will be swept away. The abstraction is more permanent than the reality.
+-

Very well put. Actually, the same misconceptions apply to computer
coding as to ASIC coding, even within object-oriented programming such
as using C++.  People believe that they must create class libraries of
more or less general-purpose code to be able to re-use it, whereas the
big gain with object-oriented programming with regard to reuse is IMHO
(1) that it's easier to understand what a piece of code does, and (2)
that pieces (objects) can be lifted out and replaced without
side-effects spreading beyond control.

Of course neither VHDL nor Verilog is object-orented in a way that
promotes this kind of reuse, while they do support the reuse of
descriptions of circuits that are being reused. However, if you use
VHDL at abstraction levels above RTL, and do transformations to RTL
code that involve the design of technology-related details,
higher-level code can be reused for new technologies (retagetting).

---
        Fredrik :Ostman
      Advanced Technology Research -- CAE
    Ellemtel Telecommunications Laboratories
  Box 1505, S-125 25 :ALVSJ:O, Stockholm, Sweden (dots go on top)



Tue, 08 Oct 1996 19:50:55 GMT  
 code reuse
Hi,

Is there any source from where I can get/buy
the source code(LEX & YACC based or C) or
an API library to parse the VHDL or Verilog
HDL files.

Thanks

Chandra

415.324.5176



Wed, 16 Oct 1996 08:52:35 GMT  
 
 [ 5 post ] 

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