Problems with PIC Designer (Composer) 4.3 
Author Message
 Problems with PIC Designer (Composer) 4.3

   I have been working on a circuit which I would like to implement in an FPGA
(Xilinx 4003). I have run into a problem with PIC Designer that seems to crop
up when multiple sources drive a single bus through tristate buffers.  I have
narrowed down the troublesome code to the two modules I include at the end of
this post. The circuit synthesizes fine, but when I get to the "Compile and
Optimize" stage in PIC designer, plcomp complains about "Redeclaration of
symbol b_0_" (and b_1_ ... b_7_). I checked the "Known Problems and
Solutions", but couldn't find anything related to this problem. There was a
section about tristate buffers causing problems with functional simulation,
but the problem here seems to be that the synthesizer is generating incorrect
DSL source!

   Anyone have similar experiences? Have I missed something? I've tried
various synthesizer options and Verilog source modifications to no avail.
Thanks in advance to anyone who can help. I would prefer responses via email

post will be fine as well. Thanks again. Here's the troublesome Verilog
source:

-----

// Module broken
//
// This is similar to a 74*245, except that there are 2 a busses connected
// to a single b bus. This is the module that causes the problem.
module broken(a1, a2, b, dir, g1, g2);
inout [7:0] a1;
inout [7:0] a2;
inout [7:0] b;
input dir;
input g1;
input g2;

tribuf buf1(a1, b, dir, g1);
tribuf buf2(a2, b, dir, g2);

endmodule

-----

// Module tribuf
//
// Implementation of the tristate buffer used in module broken.
module tribuf(a, b, dir, g);
inout [7:0] a;
inout [7:0] b;
input dir;
input g;

assign a = ((g == 0) && (dir == 1)) ? b : 8'bz;
assign b = ((g == 0) && (dir == 0)) ? a : 8'bz;

endmodule



Wed, 19 Mar 1997 10:23:53 GMT  
 
 [ 1 post ] 

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