Tetramax Remodelling/ATPG transistor level tool 
Author Message
 Tetramax Remodelling/ATPG transistor level tool

Hi,

I have a circuit with several blocks. The main clock line pass though a
block that should be skipped
(black box) for calculating the fault coverage.
So I defined this module as black box, and I would like to remodel
this block in a way that the pin clk_in is connected with buffer to the
clk_out, in this
way my clock line will pass through this block even if all the logic is
skipped and my scan flip flop
will receive a clock. How can I d this ?

Does someone know a ATPG at transistor level or switch model instead of
gate level ?
Tetramax is an ATPG at gate level (nand,and,or,...) and I think it does
not support
the transistor primitives ...(a NAND is a NAND and not 4 CMOS
transistors)

THanks a lot
GPo

--
Gianpaolo Pontarolo
IC Design and Test Group
Swiss Federal Institute of Technology Zuerich
Switzerland



Sat, 11 Sep 2004 00:29:48 GMT  
 Tetramax Remodelling/ATPG transistor level tool


Quote:

>Hi,

>I have a circuit with several blocks. The main clock line pass though a
>block that should be skipped
>(black box) for calculating the fault coverage.

If you model something as a black box you may get downstream X states
because data doesn't propagate through correctly.

Quote:
>So I defined this module as black box, and I would like to remodel
>this block in a way that the pin clk_in is connected with buffer to the
>clk_out, in this
>way my clock line will pass through this block even if all the logic is
>skipped and my scan flip flop
>will receive a clock. How can I d this ?

I have used FASTSCAN not Tetramax but I would expect that Tetramax can
do much of what FASTSCAN does. You could model this block using
'primitive' constructs. The constructs are somewhat limited. I am not
aware of anything lower than logic gates. This goes into the ATG file
which is supplied by your library vendor. Have you asked Synopsis?
Have you checked SOLVNET?

Quote:

>Does someone know a ATPG at transistor level or switch model instead of
>gate level ?
>Tetramax is an ATPG at gate level (nand,and,or,...) and I think it does
>not support
>the transistor primitives ...(a NAND is a NAND and not 4 CMOS
>transistors)

>THanks a lot
>GPo

--
Andy Botterill


Sat, 11 Sep 2004 03:12:16 GMT  
 Tetramax Remodelling/ATPG transistor level tool
Yes it is true if a fix a black box for a module the outputs will be
always X.
But if I does not fix a model to a black box, how can I easy remodel a
block ...with TetraMax primitives ?
Have I to generate a verilog netlist for the module I want to remodel
and overwrite the main netlist ?

What is the correct way to remodel a block/module with TetraMax ?

Thanks
GPo

Quote:



> >Hi,

> >I have a circuit with several blocks. The main clock line pass though a
> >block that should be skipped
> >(black box) for calculating the fault coverage.

> If you model something as a black box you may get downstream X states
> because data doesn't propagate through correctly.

> >So I defined this module as black box, and I would like to remodel
> >this block in a way that the pin clk_in is connected with buffer to the
> >clk_out, in this
> >way my clock line will pass through this block even if all the logic is
> >skipped and my scan flip flop
> >will receive a clock. How can I d this ?

> I have used FASTSCAN not Tetramax but I would expect that Tetramax can
> do much of what FASTSCAN does. You could model this block using
> 'primitive' constructs. The constructs are somewhat limited. I am not
> aware of anything lower than logic gates. This goes into the ATG file
> which is supplied by your library vendor. Have you asked Synopsis?

> Have you checked SOLVNET?

> >Does someone know a ATPG at transistor level or switch model instead of
> >gate level ?
> >Tetramax is an ATPG at gate level (nand,and,or,...) and I think it does
> >not support
> >the transistor primitives ...(a NAND is a NAND and not 4 CMOS
> >transistors)

> >THanks a lot
> >GPo

> --
> Andy Botterill

--
Gianpaolo Pontarolo
IC Design and Test Group
Swiss Federal Institute of Technology Zuerich
Switzerland


Sat, 11 Sep 2004 16:12:08 GMT  
 
 [ 3 post ] 

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