I have a clock divider where I need to divide the input clock frequency
by a facotor of 4. The input clock "mclk" is frequency divided by 2 to
generate "clk1" which in turn is frequency divided to generate "clk2".
Is there a way of telling the Synopsys Design Analyzer to fix the hold
time violation wrt. the generated clock "clk1" also. This is required
for generating a clean "clk2".

Thanks in advance,
Manjunath

You should be able to use the create_generated_clock command on the
output of the second dividing flop, with a '-divide_by 4' option.
Check the manpage for create_generated_clock for some examples on how
this command works.  Basically you just give it the source clock which
gets divided down, the place where you want the clock created, and
what modification (division, multiplication, etc.) will be performed
on the source clock:

create_generated_clock -name clk2 -source mclk -divide_by 4 find(pin,
FLOP2_reg/Q)

or in Tcl (which I greatly prefer):

create_generated_clock -name clk2 -source mclk -divide_by 4 [get_pins
FLOP2_reg/Q]

 - Chris