Questions about LRM 
Author Message
 Questions about LRM

I am writing a Verilog analysis system, and I came across a number of
things that are not clear in the Verilog LRM.
The following questions relate to IEEE Std 1364-1995.

Section 12.1, p. 136:
The grammar indicates that complex port expressions such as:
  module bar(.foo({a,b}));
  can be used.  Is this true, or is this an error in the grammar?
  (Look at the two possible expansions of the nonterminal "port")

Section 4.1.9, p. 33:
&& and || are not explicitly defined for any data type!  I assume that they
work the way they do in C.  However, how are && and || to be interpreted for
reals?  I assume that if A is a real argument to one of these, then it can be
evaluated as (A != 0.0).  There is a (weak) statement defining !A as (A==0.0).

Section 2.5.1, p. 8 and section 4.1.6, p. 32:
The default width of a based integer without a size is at least 32 bits, but
implementations are free to use more.  However, the examples on p. 32 make
sense only if the size is exactly 32 bits.  How much Verilog code would
break if the default size for integers was 64 bits instead?

Section 3.9.1 - 3.9.2, p. 25:
What happens if a real number and based register are used in an operation?
e.g.:
  reg[15:0] a,b;
  real c,d;

     a = 16'h01X3;
     c = 3.14;

     b = a + c; // Is result X due to X's in a?
     d = a + c; // Is result zero (due to X's being converted) or 262.14?

Section 4.3, p. 42:
"The min:typ:max format can be used wherever expressions may appear".
How, then, are all the operators defined?
+ and - are obvious, but what about > or <?  Can simple expressions be
mixed with mintypmax?  e.g. does 3+(1:2:4) have any meaning?

Section 16:
What is the relative priority of multiline comments and compiler directives?
e.g.:

/*
`define foo bar
*/

Does foo get defined or not?

Similarly, when the preprocessor is skipping text due to a `ifdef whose
test symbol is not defined, should it respect `include and other directives?
(It must examine `ifdef, `else and `endif to nest properly, but this is only
stated in the explanatory note 2 on p. 223!)
e.g.:

`define foo bar
`ifdef foo
`else
`include "otherfile"
`endif
// Must "otherfile" be opened and read in?  It might contain:
`endif
`ifdef gloob



Mon, 10 Jun 2002 03:00:00 GMT  
 Questions about LRM

Quote:

> I am writing a Verilog analysis system, and I came across a number of
> things that are not clear in the Verilog LRM.
> The following questions relate to IEEE Std 1364-1995.

> Section 12.1, p. 136:
> The grammar indicates that complex port expressions such as:
>   module bar(.foo({a,b}));
>   can be used.  Is this true, or is this an error in the grammar?
>   (Look at the two possible expansions of the nonterminal "port")

yup - some bits of foo get hooked up to a and some bits get hooked up to b

Quote:
> Section 4.1.9, p. 33:
> && and || are not explicitly defined for any data type!  I assume that they
> work the way they do in C.  However, how are && and || to be interpreted for
> reals?  I assume that if A is a real argument to one of these, then it can be
> evaluated as (A != 0.0).  There is a (weak) statement defining !A as (A==0.0).

I think that anywhere a true-false falue is required (!, &&, ||, for(), while() etc
and you don't present a value (multi-bit values, reals etc) then they get converted
to 1 bit by means of an implcit '!=0. This has interesting results in the presence
of Xs because the LRMs explanation of == and != is at odds with existing practice
(verilog, vcs etc) for exampole the LRM sais that 2'b1x == 2'b0x produces 1'x while
verilog/vcs recognise that it could be equal and is 1'b0 - so for example
"(2'b1x || ....)" returns 1'bx in the LRM but 1'b1 in reality (because 2;b1x != 2'b00
returns 1'b1)

Quote:
> Section 4.3, p. 42:
> "The min:typ:max format can be used wherever expressions may appear".
> How, then, are all the operators defined?
> + and - are obvious, but what about > or <?  Can simple expressions be
> mixed with mintypmax?  e.g. does 3+(1:2:4) have any meaning?

think of (::) as an operator like (?:) with it's own precedence

Quote:

> Section 16:
> What is the relative priority of multiline comments and compiler directives?
> e.g.:

> /*
> `define foo bar
> */

> Does foo get defined or not?

no

        Paul Campbell



Tue, 11 Jun 2002 03:00:00 GMT  
 Questions about LRM

Quote:

> I think that anywhere a true-false falue is required (!, &&, ||, for(), while() etc
> and you don't present a value (multi-bit values, reals etc) then they get converted
> to 1 bit by means of an implcit '!=0. This has interesting results in the presence
> of Xs because the LRMs explanation of == and != is at odds with existing practice
> (verilog, vcs etc) for exampole the LRM sais that 2'b1x == 2'b0x produces 1'x while
> verilog/vcs recognise that it could be equal and is 1'b0 - so for example
> "(2'b1x || ....)" returns 1'bx in the LRM but 1'b1 in reality (because 2;b1x != 2'b00
> returns 1'b1)

The LRM 1364-1995 is wrong.
It will be corrected in 1364-2000.
The new wording will be:

"For the logical equality and logical inequality operators (== and !=), if, due to unknown or
high-impedance bits in the operands, the relation is ambiguous, then the result shall be a one bit
unknown value (x)."

--

************************************************************************

Motorola Semiconductor Israel, Ltd.     Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL      Fax #: +972 9 9522444
http://www.motorola-semi.co.il/
************************************************************************



Thu, 13 Jun 2002 03:00:00 GMT  
 Questions about LRM

Quote:

> The LRM 1364-1995 is wrong.
> It will be corrected in 1364-2000.
> The new wording will be:

> "For the logical equality and logical inequality operators (== and !=), if, due to unknown or
> high-impedance bits in the operands, the relation is ambiguous, then the result shall be a one bit
> unknown value (x)."

(yeah I think I was the one to point it out to Mike :-)
BTW I beleive a good way to describe the current VCS/Verilog
implementations that works reliably in the presence of Xs is:

        a != b is exactly |(a^b)
        a == b is exactly &(a^~b)

Also !a (in the context of multi-bit operations) seems to mean a==0
and seems to behave around Xs as described above (as I pointed out
before similar things happen around && and ||)

        Paul Campbell



Sat, 15 Jun 2002 03:00:00 GMT  
 
 [ 4 post ] 

 Relevant Pages 

1. Question about LRM: indexed name, attrib_name

2. Question regarding LRM 5.95 7.6(19)

3. diff Ada83-LRM Ada9X-LRM

4. Verilog LRM 2.0 question

5. OVI LRM Questions

6. Aggregate Selection With Variables (LRM Question)

7. LRM question

8. LRM question - access types and concurrency

9. COBOL 74 LRM Needed

10. LRM sec 13.4.1

11. LRM Sec 10.2.1

12. LRM for Verilog 2001 and System Verilog

 

 
Powered by phpBB® Forum Software