case statement flipflop statement 
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 case statement flipflop statement

Can somebody tell me why this generates TFFE rather than DFFE.  What I
want is a group of read/write registers are varying sizes that are used
to drive some combinational logic.  I know the always statement is ok
but I have a problem when I add the case statment.  I am using
MAXplusII 9.3 to compile.  What am I doing wrong?

Thanks
BOB

module topV(
btclk,
sdregwr,
sdregrd,
breset,
paa,
spd_sclout,
spd_sdaout,
dbus);

//inputs
input btclk sdregwr, sdregrd, breset;
input [2:0] paa; // pa bits 6 to 3
input [3:0] mahi; // ma bits 27 to 24
input [1:0] mamid;// ma bits 11 and 12

// bidirectional bits

inout [6:0]dbus;
reg[6:0]dout;
wire [6:0]din = dbus;

inout spd_sclout;
inout spd_sdaout;

//Registers

reg [6:0] d1b1mr;
reg [3:0] d1b2mr;
reg [6:0] d2b1mr;
reg [3:0] d2b2mr;
reg [4:0] d1amux;
reg [5:0] d2amux;
reg [3:0] spdreg;

wire spd_sclin = spd_sclout;
wire spd_sdain = spd_sdaout;

assign spd_sdaout = spdreg[3] ? 1'b0 : 1'bz;
assign spd_sclout = spdreg[2] ? 1'b0 : 1'bz;

assign dbus = sdregrd ?  dout : 7'bzzzzzzz;


// initialize registers
if (~breset)begin

d1b1mr = 7'b0000000;
d1b2mr = 4'b0000;
d2b1mr = 7'b0000000;
d2b2mr = 4'b0000;
d1amux = 5'b00000;
d2amux = 6'b000000;
spdreg = 4'b0000;

end

// write to registers
if (!sdregwr)begin

                        case (paa)

                3'b000:  d1b1mr = din;
                3'b001:  d1b2mr = din;
                3'b010:  d2b1mr = din;
                3'b011:  d2b2mr = din;
                3'b100:  d1amux = din;
                3'b101:  d2amux = din;
                3'b110:  spdreg[3:2] = {spd_sclin,spd_sdain};
                //3'b111: ;

                endcase
end

// Read from Registers

else if(!sdregrd )
        begin
        case (paa)
        3'b000: dout= d1b1mr;
        3'b001: dout = {3'b000, d1b2mr};
        3'b010: dout = d2b1mr;
        3'b011: dout = {3'b000, d2b2mr};
        3'b100: dout = {2'b00, d1amux};
        3'b101: dout = {1'b0, d2amux};
        3'b110: dout = {3'b000, spdreg};
        3'b111: dout = 7'bxxxxxxx;
        endcase

        end

end

endmodule

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Tue, 17 Dec 2002 03:00:00 GMT  
 case statement flipflop statement

did you try using an "else if" statement instead of an "if" in line:

Quote:
> if (!sdregwr)begin

hope that helps...


Quote:
> Can somebody tell me why this generates TFFE rather than DFFE.  What I
> want is a group of read/write registers are varying sizes that are used
> to drive some combinational logic.  I know the always statement is ok
> but I have a problem when I add the case statment.  I am using
> MAXplusII 9.3 to compile.  What am I doing wrong?

> Thanks
> BOB

> module topV(
> btclk,
> sdregwr,
> sdregrd,
> breset,
> paa,
> spd_sclout,
> spd_sdaout,
> dbus);

> //inputs
> input btclk sdregwr, sdregrd, breset;
> input [2:0] paa; // pa bits 6 to 3
> input [3:0] mahi; // ma bits 27 to 24
> input [1:0] mamid;// ma bits 11 and 12

> // bidirectional bits

> inout [6:0]dbus;
> reg[6:0]dout;
> wire [6:0]din = dbus;

> inout spd_sclout;
> inout spd_sdaout;

> //Registers

> reg [6:0] d1b1mr;
> reg [3:0] d1b2mr;
> reg [6:0] d2b1mr;
> reg [3:0] d2b2mr;
> reg [4:0] d1amux;
> reg [5:0] d2amux;
> reg [3:0] spdreg;

> wire spd_sclin = spd_sclout;
> wire spd_sdain = spd_sdaout;

> assign spd_sdaout = spdreg[3] ? 1'b0 : 1'bz;
> assign spd_sclout = spdreg[2] ? 1'b0 : 1'bz;

> assign dbus = sdregrd ?  dout : 7'bzzzzzzz;


> // initialize registers
> if (~breset)begin

> d1b1mr = 7'b0000000;
> d1b2mr = 4'b0000;
> d2b1mr = 7'b0000000;
> d2b2mr = 4'b0000;
> d1amux = 5'b00000;
> d2amux = 6'b000000;
> spdreg = 4'b0000;

> end

> // write to registers
> if (!sdregwr)begin

> case (paa)

> 3'b000:  d1b1mr = din;
> 3'b001:  d1b2mr = din;
> 3'b010:  d2b1mr = din;
> 3'b011:  d2b2mr = din;
> 3'b100:  d1amux = din;
> 3'b101:  d2amux = din;
> 3'b110:  spdreg[3:2] = {spd_sclin,spd_sdain};
> //3'b111: ;

> endcase
> end

> // Read from Registers

> else if(!sdregrd )
> begin
> case (paa)
> 3'b000: dout= d1b1mr;
> 3'b001: dout = {3'b000, d1b2mr};
> 3'b010: dout = d2b1mr;
> 3'b011: dout = {3'b000, d2b2mr};
> 3'b100: dout = {2'b00, d1amux};
> 3'b101: dout = {1'b0, d2amux};
> 3'b110: dout = {3'b000, spdreg};
> 3'b111: dout = 7'bxxxxxxx;
> endcase

> end

> end

> endmodule

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Sat, 21 Dec 2002 03:00:00 GMT  
 
 [ 2 post ] 

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