nested cases? 
Author Message
 nested cases?

I'm told nested case statements are not allowed by the Verilog standard. The
books I have make no mention either way. If I try it it seems to be accepted
and works. What's the real story?

Thanks,
Tom C.



Sat, 10 Sep 2005 07:15:59 GMT  
 nested cases?

Quote:
> I'm told nested case statements are not allowed by the Verilog standard.

Not according to the one I've read.  Each case branch controls a
single Verilog procedural statement.  If that's a begin..end block,
it can then contain any procedural code you like.  No problem
other than legibility:

reg [1:0] a, b;

...
  case (a)
    2'd0:
      b = 3;
    2'd1:
      b = 2;
    2'd2:
      begin
        b = ~b;
        case (b)
          2'd1:
            $display("2,2");
          default:
            $display("hello");
        endcase
      end
    default: ;
  endcase

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Sat, 10 Sep 2005 16:26:46 GMT  
 nested cases?

Quote:

> I'm told nested case statements are not allowed by the Verilog standard. The
> books I have make no mention either way. If I try it it seems to be accepted
> and works. What's the real story?

Whoever told you this is obviously confused.  A case statement can contain
any other statement, including another case statement.

Perhaps they ran into a limitation in some FPGA synthesis tool or
something and assumed it was a language limitation.



Mon, 12 Sep 2005 07:52:38 GMT  
 nested cases?
i use verilog for modelling & verification. I have used nested
case statements (3-4 case statements) never faced any issues.
Quote:

> I'm told nested case statements are not allowed by the Verilog standard. The
> books I have make no mention either way. If I try it it seems to be accepted
> and works. What's the real story?

> Thanks,
> Tom C.



Mon, 12 Sep 2005 22:45:28 GMT  
 
 [ 4 post ] 

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