Creating a resistor model for system level synthesis 
Author Message
 Creating a resistor model for system level synthesis

How can I create a simulation model for a resistor that is used
as a series resistor in a schematic (whose netlist is then
extracted into Verilog for simulation)? The resistor can be
placed in any orientation such that it can have drivers on
either end or both sides; as a series resistor we just want
it to pass the value through from the one active driver (determined
by the design state).

Originally we had connected two buffers back to back like this:

module RESISTOR(R1,R2) ; // resistor model
        inout R1, R2 ;

        buf (pull1,pull0) p1(R1,R2) ;
        buf (pull1,pull0) p2(R2,R1) ;
endmodule

This has problems with other drivers conflicting and causing
the net to go to X.

Optimally, the model should also be able to be used in
a pullup/down situation, again without concern with which side
is connected to the supply.

Any suggestions would be appreciated. Thanks,
Lauren Baker
Cabletron Systems



Sun, 05 Jan 1997 05:59:51 GMT  
 Creating a resistor model for system level synthesis

Quote:

>How can I create a simulation model for a resistor that is used
>as a series resistor in a schematic (whose netlist is then
>extracted into Verilog for simulation)?
>Optimally, the model should also be able to be used in
>a pullup/down situation, again without concern with which side
>is connected to the supply.
>Any suggestions would be appreciated. Thanks,

Perhaps this should be in an FAQ for this group...

I wrote this based on a suggestion here a few months back; works in all of
those cases you mentioned

module resqtr(a,b);
inout a;
inout b;

wire a;
wire b;

        rtran r(a,b);

endmodule

--

CS Grad Student, UNC Chapel Hill.   W: +1 919 962 1845   Carrboro NC 27510

"Theatre is life, film is art, television is furniture."



Sun, 05 Jan 1997 12:22:45 GMT  
 Creating a resistor model for system level synthesis

Quote:
>How can I create a simulation model for a resistor that is used
>as a series resistor in a schematic (whose netlist is then
>extracted into Verilog for simulation)? The resistor can be
>placed in any orientation such that it can have drivers on
>either end or both sides; as a series resistor we just want
>it to pass the value through from the one active driver (determined
>by the design state).

>Originally we had connected two buffers back to back like this:

>module RESISTOR(R1,R2) ; // resistor model
>        inout R1, R2 ;

>        buf (pull1,pull0) p1(R1,R2) ;
>        buf (pull1,pull0) p2(R2,R1) ;
>endmodule

 Try this:

module RESISTOR(R1,R2) ; // resistor model
        inout R1, R2 ;

       rtran p1(R2,R1) ;

endmodule

---

 ___________________________________________________________________
 Jim Stein                     phone: (508) 266-4554
 ascom Timeplex APBU           fax:   (508) 264-4999
 289 Great Road, Suite 209    

 ___________________________________________________________________



Mon, 06 Jan 1997 05:44:39 GMT  
 Creating a resistor model for system level synthesis

Quote:

>How can I create a simulation model for a resistor that is used
>as a series resistor in a schematic (whose netlist is then
>extracted into Verilog for simulation)? The resistor can be

We try to avoid this like the plague, because it surely doesn't help
performance any. But sometimes, due to histerical reasons, these kinds of
constructs have to be dealt with. This is what we use to pacify the
schematic netlister.

module netalias (io, io); inout io; endmodule

Ideally, this useless construct would be recognized by the simulator and
optimized out (hint hint), and both ends would be treated as one and the same.

        -Kartik



Tue, 07 Jan 1997 11:37:42 GMT  
 Creating a resistor model for system level synthesis
|> How can I create a simulation model for a resistor that is used
|> as a series resistor in a schematic (whose netlist is then
|> extracted into Verilog for simulation)? The resistor can be
|> placed in any orientation such that it can have drivers on
|> either end or both sides; as a series resistor we just want
|> it to pass the value through from the one active driver (determined
|> by the design state).
|>
|> Originally we had connected two buffers back to back like this:
|>
|>
|> module RESISTOR(R1,R2) ; // resistor model
|>         inout R1, R2 ;
|>
|>         buf (pull1,pull0) p1(R1,R2) ;
|>         buf (pull1,pull0) p2(R2,R1) ;
|> endmodule
|>
|> This has problems with other drivers conflicting and causing
|> the net to go to X.
|>
|> Optimally, the model should also be able to be used in
|> a pullup/down situation, again without concern with which side
|> is connected to the supply.
|>

If these are really the only cases you care about (series and pullup/down),
I'd suggest using a tran.  Something like this:

module RESISTOR(R1,R2);

  inout R1,R2;

  tran t1 (R1,R2);

endmodule

-- bob wood
   data general corp.



Wed, 08 Jan 1997 21:23:31 GMT  
 Creating a resistor model for system level synthesis


|> >How can I create a simulation model for a resistor that is used
|> >as a series resistor in a schematic (whose netlist is then
|> >extracted into Verilog for simulation)? The resistor can be
|>
|> We try to avoid this like the plague, because it surely doesn't help
|> performance any. But sometimes, due to histerical reasons, these kinds of
|> constructs have to be dealt with. This is what we use to pacify the
|> schematic netlister.
|>
|> module netalias (io, io); inout io; endmodule
|>
|> Ideally, this useless construct would be recognized by the simulator and
|> optimized out (hint hint), and both ends would be treated as one and the same.

Verilog-XL does treat this as one and the same.
 See the manual section on  "Port Collapsing"

--
___________________________________________________________

Cadence Design, 270 Billerica Rd., Chelmsford MA 01824-4140
"I used to have Time. Now I have Twins"
___________________________________________________________



Sat, 11 Jan 1997 03:07:04 GMT  
 Creating a resistor model for system level synthesis
Kartik> We try to avoid this like the plague, because it surely doesn't help
Kartik> performance any. But sometimes, due to histerical reasons, these kinds of
Kartik> constructs have to be dealt with. This is what we use to pacify the
Kartik> schematic netlister.

Kartik> module netalias (io, io); inout io; endmodule

Kartik> Ideally, this useless construct would be recognized by the simulator and
Kartik> optimized out (hint hint), and both ends would be treated as one and the same.

This is a little off the subject but I would like to deal with the issue
of multiple ports on a net with the above being one way to try to
implement this.  The problem with this type of construct is getting out
of the Verilog world into generic hierarchical netlisting.  What this
violates is the uniqueness of the port names as port 1 and port 2 are
both named io.  Another technique which is used is the following:

module netalias (in, out);
  input in;
  output out;
  assign out = in;
endmodule

While this has a behavi{*filter*}constuct it allows synthesis tools to
optimize away a buffer or resistor or the like.  When read into the
system this module is interpretted as net out with ports in and out.

It is indeed unfortunate that Verilog does not support multiple ports on
a net or net aliasing (and that is has single name space for instances
and nets).  If it had followed the five-box model which is followed for
EDIF or CFI then it could be a more portable description of structural
netlists (if character set restrictions were removed).

--
================================================================
Rich Blinne
NCR Microelectronic Products Division
AT&T Global Information Solutions
2001 Danfield Ct.       |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~




Sun, 12 Jan 1997 22:48:23 GMT  
 Creating a resistor model for system level synthesis

Quote:

>Kartik> module netalias (io, io); inout io; endmodule

>This is a little off the subject but I would like to deal with the issue
>of multiple ports on a net with the above being one way to try to
>implement this.  The problem with this type of construct is getting out
>of the Verilog world into generic hierarchical netlisting.  What this
>violates is the uniqueness of the port names as port 1 and port 2 are
>both named io.  Another technique which is used is the following:

Hmm? The internal "io" port is used solely for the jumpering. It has no
real meaning in the schematic. In the instantiation of the module, the real
names will be passed used. So you don't lose any uniqueness or anything.

Quote:
>module netalias (in, out);
>  input in;
>  output out;
>  assign out = in;
>endmodule

>While this has a behavi{*filter*}constuct it allows synthesis tools to
>optimize away a buffer or resistor or the like.  When read into the
>system this module is interpretted as net out with ports in and out.

Yes but this doesn't handle bidirectionality.

Quote:
>It is indeed unfortunate that Verilog does not support multiple ports on
>a net or net aliasing (and that is has single name space for instances
>and nets).  If it had followed the five-box model which is followed for
>EDIF or CFI then it could be a more portable description of structural
>netlists (if character set restrictions were removed).

Yes, this is sorely lacking. Wish something like it were in OVI 2.0. Still,
this doesn't prevent vendors from internally optimizing these constructs
out...

--
Kartik Subbarao, Workstation Systems Division, Hewlett-Packard



Mon, 13 Jan 1997 04:01:51 GMT  
 Creating a resistor model for system level synthesis
I am a little concerned that most of the responces
to the resistor model have been aimed at the simplest
model.  Some of the them even try to eliminate it
by making it appear to be a net.  However, in many
cases it is necessary to model its behavior carefully.

I recall working on an ASIC where an external resistor
was intended to hold the write signal high in an
arbatrated bus.  Each ASIC driving the bus was supposed
to drive the write signal high before releasing it with
the resistor dominating only when the bus was not owned.
One of the ASICs didn't and a zero propagation delay
resistor disguised the problem in the system simulation.
We then devised a much more sophisticated resistor but
only after a $100,000 mistake.

I don't think there is a universal resistor for digital
simulation purposes.

Ed



Mon, 13 Jan 1997 11:59:44 GMT  
 Creating a resistor model for system level synthesis

Quote:

>I am a little concerned that most of the responces
>to the resistor model have been aimed at the simplest
>model.  Some of the them even try to eliminate it
>by making it appear to be a net.  However, in many
>cases it is necessary to model its behavior carefully.
>One of the ASICs didn't and a zero propagation delay
>resistor disguised the problem in the system simulation.
>We then devised a much more sophisticated resistor but
>only after a $100,000 mistake.

>I don't think there is a universal resistor for digital
>simulation purposes.

No, but I think you're describing the exception and not the rule. Of course
you should be careful when using ANY model. After all, these tools can't
read your mind. But that shouldn't preclude a simulator from optimizing
out unnecessary code.

--
Kartik Subbarao, Workstation Systems Division, Hewlett-Packard



Tue, 14 Jan 1997 10:05:17 GMT  
 
 [ 12 post ] 

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