verilog equivalent to the vhdl 'length 
Author Message
 verilog equivalent to the vhdl 'length

Is there a verilog equivalent to the vhdl attribute 'length? I am trying
to extact the length from an input bus.  Unfortunately,  I cannot
parameterize the i/o of this module due to tool constraints.

Any ideas?

Mark Wartski




Sun, 01 Nov 1998 03:00:00 GMT  
 verilog equivalent to the vhdl 'length

   Is there a verilog equivalent to the vhdl attribute 'length? I am trying
   to extact the length from an input bus.  Unfortunately,  I cannot
   parameterize the i/o of this module due to tool constraints.

   Any ideas?

One:

        Use a macro, not a parameter to specify the width of the io:

module foo (a,b);

        input [`width:0] a;
        output [`width:0] b;
        wire [`width:0] a,b;

        foo f_1 #(`width) (a,b);

endmodule

Two:
        Use perl to process your module definition, and propogate what
ever you'd like to the place you would use length.  John Williams just
posted a perl wrapper fragment from which you could start.

Three:
        Use acc_ or vpu_ routines to dynamically access your design,
and pass back the info (only useful if you only need `length at
simulation time)

        -mac

--
Michael McNamara
Silicon Sorcery  <http://www.silicon-sorcery.com>



Fri, 06 Nov 1998 03:00:00 GMT  
 
 [ 2 post ] 

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