Verilog-XL/NC-Verilog Event Order 
Author Message
 Verilog-XL/NC-Verilog Event Order

Hi,

After searching through literally 1000's of web pages (ok, actually a
couple dozen maybe) without even a glimmer of hope of finding an
answer, I'm resorting to the news group.

The situation:

We're designing Verilog behavi{*filter*}models for SRAM modules. The timing
checks are kind of involved. (Ex: Ignore address setup errors when
module-select is low unless there is also a setup error on the
module-select signal.) Anyway, to ensure that the events get processed
in the correct order, we occasionally use

x <= #0 1'b0;

a non-blocking zero delay. Add this event to the end of the current
event queue. This ensures that the timing checks will be executed
before normal processing or visa-versa depending on the situation.
Everything's fine in Verilog-XL.

BUT...

The problem:

When simulated with NC-Verilog, non-blocking zero delays appear to be
processed instantly. Timing checks ($setup, $hold, etc.) also appear
to be executed in a different order.

Anybody know of a solution? We'd like to use the same models for
Verilog-XL and NC-Verilog (obviously). Any compile time/run-time
options for NC-Verilog to ensure event timing compatibility?

Using

Verilog-XL
NC-Verilog

BTW, the <installation_directory>/tools/inca/files/README file states

"To ensure accuracy, the timing features have gone through rigorous
testing
against Verilog-XL with a large number of real testcases. This is key
for
the timing improvements, as these tend to be complex in operation.
Timing
equivalency with Verilog-XL is assured by the level of testing
applied."

So I'm sure there's a solution somewhere ;-).

D.Bailey



Sat, 14 Aug 2004 09:56:49 GMT  
 Verilog-XL/NC-Verilog Event Order

Refer to the attached article and Janick Bergerons book "Writting
Testbenches" and you will see that there is know need to ever use #0
delays.

Graeme  

Quote:

> Hi,

> After searching through literally 1000's of web pages (ok, actually a
> couple dozen maybe) without even a glimmer of hope of finding an
> answer, I'm resorting to the news group.

> The situation:

> We're designing Verilog behavi{*filter*}models for SRAM modules. The timing
> checks are kind of involved. (Ex: Ignore address setup errors when
> module-select is low unless there is also a setup error on the
> module-select signal.) Anyway, to ensure that the events get processed
> in the correct order, we occasionally use

> x <= #0 1'b0;

> a non-blocking zero delay. Add this event to the end of the current
> event queue. This ensures that the timing checks will be executed
> before normal processing or visa-versa depending on the situation.
> Everything's fine in Verilog-XL.

> BUT...

> The problem:

> When simulated with NC-Verilog, non-blocking zero delays appear to be
> processed instantly. Timing checks ($setup, $hold, etc.) also appear
> to be executed in a different order.

> Anybody know of a solution? We'd like to use the same models for
> Verilog-XL and NC-Verilog (obviously). Any compile time/run-time
> options for NC-Verilog to ensure event timing compatibility?

> Using

> Verilog-XL
> NC-Verilog

> BTW, the <installation_directory>/tools/inca/files/README file states

> "To ensure accuracy, the timing features have gone through rigorous
> testing
> against Verilog-XL with a large number of real testcases. This is key
> for
> the timing improvements, as these tend to be complex in operation.
> Timing
> equivalency with Verilog-XL is assured by the level of testing
> applied."

> So I'm sure there's a solution somewhere ;-).

> D.Bailey

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Graeme Cunningham - EngD Research Engineer                  
Motorola NCSG, Livingston, UK                    
Tel : +44(0)1506 47 3377(Motorola) +44(0)1506 469 300
(ISLI)                      
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Verification is Fun!!!

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Sat, 14 Aug 2004 20:32:22 GMT  
 
 [ 2 post ] 

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