Minimum, Typical, Maxmimum Delays
Author Message
Minimum, Typical, Maxmimum Delays

(tin problems, sigh) ...

I've checked Thomas & Moorby (4th edition, page 154) and IEEE 1364-1995
(pp.  84, 165-ish) and I'm still not quite certain about how min-typ-max
delays work. Could some kind soul enlighten me?

For example, in:

always value1 = # (2:10:17) 4'h5 ;

... when is the minimum delay used? The typical? The maximum? Is the delay
drawn randomly from a distribution defined by those three numbers? How does
this work? Finally, what physical phenomenon is typically modelled by a
min-typ-max delay?

- Wes

Tue, 26 Nov 2002 03:00:00 GMT
Minimum, Typical, Maxmimum Delays

Quote:

> (tin problems, sigh) ...

> I've checked Thomas & Moorby (4th edition, page 154) and IEEE 1364-1995
> (pp.  84, 165-ish) and I'm still not quite certain about how min-typ-max
> delays work. Could some kind soul enlighten me?

> For example, in:

>         always value1 = # (2:10:17) 4'h5 ;

> ... when is the minimum delay used? The typical? The maximum? Is the delay
> drawn randomly from a distribution defined by those three numbers? How does
> this work? Finally, what physical phenomenon is typically modelled by a
> min-typ-max delay?

If you do nothing the typical delay is used, but there are run-time
flags "-mindelays" etc (check your development system's docs for more
info) that that are used to change which is used for a particular environment

Paul Campbell

Tue, 26 Nov 2002 03:00:00 GMT
Minimum, Typical, Maxmimum Delays
Hi,

Quote:
> I've checked Thomas & Moorby (4th edition, page 154) and IEEE 1364-1995
> (pp.  84, 165-ish) and I'm still not quite certain about how min-typ-max
> delays work. Could some kind soul enlighten me?

> For example, in:

> always value1 = # (2:10:17) 4'h5 ;

These delays are often backannotated into a design using an SDF file
(Standard Delay Format, I think...).  You have given an example where the
delay triplets are coded directly into the verilog code.  What are you
applying these various delays to?  (FPGA, ASIC, ???)

Quote:
> ... when is the minimum delay used?

If applied to timing checks on an ASIC or FPGA, you use minimum delays
to check hold times.  Min delays will define the performance of your
device under the fastest conditions possible.

Quote:
> The typical? The maximum?

You can use max delays to check for setup timing.  (this tells you the
maximum speed your device will run, under worst case conditions)
Typical delays are of limited value,
since it is usually the extremes that you want to check.

Quote:
> Is the delay
> drawn randomly from a distribution defined by those three numbers?

Nope.  You can define which delay set you wish to use.

Quote:
> How does
> this work?

a person reads in a netlist and then backannotates it with SDF.  There
will either be one SDF file for each delay case, or you will specify
the min/typ/max columns to be used from a single SDF file (one SDF file
can define 3 delay cases...min/typ/max).  Using simulator options, you
select the delays to simulate with.  STA (static timing analysis) tools
usually require SDF files to check timing, and again you can select the
min/typ/max delays which you want to use.

Quote:
> Finally, what physical phenomenon is typically modelled by a
> min-typ-max delay?

Generally, every chip has best and worst PVT points defined.  Process.
Voltage.  Temperature.  These are the three main factors which effect
delays through semiconductors.  Process will be dictated by the actual
semiconductor manufacturer.  They will define limits to their process,
and any given part may fall anywhere inside of those limits.  For example,
you could have a device that has fast silicon, or slower silicon, just
because it was manufactured under slightly different conditions.  Voltage
also affects speed.  Higher voltage, faster parts.  Temperature is the
last major factor.  Higher temperature means lower speed (and reliability).

All of these factors are pulled together and modeled as minimum, typical,
and maximum delays.

Cheers,
Jeremy

Tue, 26 Nov 2002 03:00:00 GMT
Minimum, Typical, Maxmimum Delays

writes

Quote:
>a person reads in a netlist and then backannotates it with SDF.  There
>will either be one SDF file for each delay case, or you will specify
>the min/typ/max columns to be used from a single SDF file (one SDF file
>can define 3 delay cases...min/typ/max).  Using simulator options, you
>select the delays to simulate with.  STA (static timing analysis) tools
>usually require SDF files to check timing, and again you can select the
>min/typ/max delays which you want to use.

Do the values in the SDF file represent the gate and track delay?
--
Andy Botterill

Wed, 27 Nov 2002 03:00:00 GMT
Minimum, Typical, Maxmimum Delays

Quote:

> Do the values in the SDF file represent the gate and track delay?

Yes.

Wed, 27 Nov 2002 03:00:00 GMT
Minimum, Typical, Maxmimum Delays

writes
Quote:

>> Thanks. Track delay is a function of inter poly capacitance which will
>> vary differently compared to gate oxide/vt etc. Is it possible that the
>> logic gate could give minimum delays whilst the track gives maximum
>> delays. Does SDF take this into account?

>Sort of.  The delay predictor takes the various factors into account,
>and computes the appropriate delays for both wires and cells.  SDF has
>sections for both interconnect and instantiated cells.  It is difficult

That's useful information.

Quote:
>to get a situation where cell delays are at a minimum, while wire delays
>are max (or visa versa), so they usually derate together.

Cell delay is a function of gate oxide dimensions and vtn/vtp. Wire
delay is a function of inter poly ( metal?) oxide thickness. These are
done by two different process stages so they could vary quite
differently. I would also expect a fab to keep gate oxide dimensions
more accurately than inter poly oxide thickness.

Quote:

>Jeremy

--
Andy Botterill

Fri, 29 Nov 2002 03:00:00 GMT
Minimum, Typical, Maxmimum Delays

Quote:
> Cell delay is a function of gate oxide dimensions and vtn/vtp. Wire
> delay is a function of inter poly ( metal?) oxide thickness. These are
> done by two different process stages so they could vary quite
> differently. I would also expect a fab to keep gate oxide dimensions
> more accurately than inter poly oxide thickness.

Both cell and wire delays are functions of many factors.  These factors
often (but not always) drift together.

What's "inter poly oxide thickness"?

Fri, 29 Nov 2002 03:00:00 GMT
Minimum, Typical, Maxmimum Delays

writes
Quote:

>Both cell and wire delays are functions of many factors.  These factors
>often (but not always) drift together.

>What's "inter poly oxide thickness"?

A track is a layer of polysilison doped to have a low resistance ( some
technologies it may be metal ) on top of an oxide layer which separates
it from other tracks or gates. The oxide that separates the polysilicon
from other layers or gates is called inter poly oxide. Its thickness
determines the capacitance per unit length of a track. This thickness is
likely to be less controlled that gate oxide thickness dimensions.
--
Andy Botterill

Fri, 29 Nov 2002 03:00:00 GMT

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