I've got:

module dff(Q,CLK,D);
        output Q;
        input  CLK,D;

        dff_udp(Q,CLK,D);
endmodule

primitive dff_udp(Q,CLK,D);
        output Q;
        input  CLK,D;
        reg    Q;

        table
        .
        .
        .
        endtable
endprimitive

How do I force Q to 1'b0 at time=0?  (initial #0 Q=1'b0;
in the module doesn't work.)

Put the initial statement in the udp, not in the module:

primitive dff_udp(Q,CLK,D);
   output Q;
   input  CLK,D;
   reg    Q;
   initial Q = 1;
   table
      // CLK D   Q   Q+
      (01)   0 : ? : 0 ;
      (01)   1 : ? : 1 ;
      (0?)   1 : 1 : 1 ;
      (0?)   0 : 0 : 0 ;
      (?0)   ? : ? : - ;
      ?   (??) : ? : - ;
   endtable
endprimitive

This example is taken (without permission) directly from the IEEE 1364
spec (page 8-8); it might be useful for you to obtain one of these.
Point your web browser at <http://stdsbbs.ieee.org/faqs/order.html>
and discover how to order; what you want is Catalog number DS5408.  It
will cost either $81 or $65, depending on whether you are an IEEE
member.

Note that this is just the approved draft standard; some might want to
wait until the official IEEE version is printed and available; however
in your case it seems waiting is not recommended! :-)

Project     Draft    Draft     Title   List          Member        Catalog
Number      Date     Version           Price         Price         Number
--------------------------------------------------------------------------
1364*       Oct-95             Verilog HDL Language Reference Manual (LRM)
                                       $81.00        $65.00        DS5408

--
Michael McNamara
DV Consulting Services, Inc.

I've got the IEEE Draft spec, the Verilog XL manuals & some
other books.

The problem is that Verilog XL doesn't propogate the above
initial assignment at time=0.  (I've tried it, and it also states
something to this effect in the manual.)  After time=0, this
Q=0 assignment is being immediately overwritten by the next event.