Code checking tool 
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 Code checking tool

I am using Model Tech's VSystem+ for Verilog simulation on a
Windows NT box; it's supposed to be a lot like Verilog XL,
which I'm assuming behaves the same way.

What I've found is that I can create an instance like

foo_definition foo_instance (
    .defined_input_signal (local_input_signal)
);

and if the local_input_signal does not exist, I do not get
a warning or error from the Verilog compiler.  Instead, the
instance is created and has an undefined value for the
corresponding input signal.

I'm not sure if this is in accordance with standard Verilog,
but it is certainly at odds with sound programming practice.

Is anyone aware of a tool that I can use to check my Verilog
code for undefined signals?  Preferrably, it will be available
for my favorite price -- free.  I'm just worried that I might
not catch all of the undefined signals during simulation.

TIA,
Mike Woodring
SW/HW Engineer
IRE

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Sat, 15 Jan 2000 03:00:00 GMT  
 Code checking tool

Quote:

>I am using Model Tech's VSystem+ for Verilog simulation on a
>Windows NT box; it's supposed to be a lot like Verilog XL,
>which I'm assuming behaves the same way.

>What I've found is that I can create an instance like

>foo_definition foo_instance (
>    .defined_input_signal (local_input_signal)
>);

>and if the local_input_signal does not exist, I do not get
>a warning or error from the Verilog compiler.  Instead, the
>instance is created and has an undefined value for the
>corresponding input signal.

>I'm not sure if this is in accordance with standard Verilog,
>but it is certainly at odds with sound programming practice.

>Is anyone aware of a tool that I can use to check my Verilog
>code for undefined signals?  Preferrably, it will be available
>for my favorite price -- free.  I'm just worried that I might
>not catch all of the undefined signals during simulation.

>TIA,
>Mike Woodring
>SW/HW Engineer
>IRE

Not free, but Verilint will check this and hundreds of other
suspicious constructs. Contact interHDL at (415) 428-4200,

Eli

--
Eli Sternheim
interHDL, Inc.
4984 El Camino Real, Suite 210
Los Altos, CA. 94022-1433
phone: 415-428-4200
fax:   415-428-4201



Sat, 15 Jan 2000 03:00:00 GMT  
 Code checking tool

Unforturnately I've found many such limitations/poor error checking from
namy of the close simulators.  I'd use the gold standard, Verilog-XL.
I've found that my students will have problems with there verilog that
were difficult to debug, but the error and warning message from -XL made
them easier to find.

Just my $0.02.

Any by the way I aggree with Eli, Verilint can help catch lost of errors
as well.

-- James

Quote:

> I am using Model Tech's VSystem+ for Verilog simulation on a

> Windows NT box; it's supposed to be a lot like Verilog XL,

> which I'm assuming behaves the same way.

> What I've found is that I can create an instance like

> foo_definition foo_instance (

>     .defined_input_signal (local_input_signal)

> );

> and if the local_input_signal does not exist, I do not get

> a warning or error from the Verilog compiler.  Instead, the

> instance is created and has an undefined value for the

> corresponding input signal.

> I'm not sure if this is in accordance with standard Verilog,

> but it is certainly at odds with sound programming practice.

> Is anyone aware of a tool that I can use to check my Verilog

> code for undefined signals?  Preferrably, it will be available

> for my favorite price -- free.  I'm just worried that I might

> not catch all of the undefined signals during simulation.

> TIA,

> Mike Woodring

> SW/HW Engineer

> IRE

> --

> Posted using Reference.COM                         http://www.reference.com
> Browse, Search and Post         Usenet and Mailing list Archive and Catalog.

> InReference, Inc. accepts no responsibility for the content of this posting.

--
-.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -....

  Verilog Instructor        
  Author "Verilog Quickstart" ISBN 0-7923-9927-7
-.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -....


Sat, 15 Jan 2000 03:00:00 GMT  
 Code checking tool

Quote:

> I am using Model Tech's VSystem+ for Verilog simulation on a
> Windows NT box; it's supposed to be a lot like Verilog XL,
> which I'm assuming behaves the same way.

> What I've found is that I can create an instance like

> foo_definition foo_instance (
>     .defined_input_signal (local_input_signal)
> );

> and if the local_input_signal does not exist, I do not get
> a warning or error from the Verilog compiler.  Instead, the
> instance is created and has an undefined value for the
> corresponding input signal.

> I'm not sure if this is in accordance with standard Verilog,
> but it is certainly at odds with sound programming practice.

> Is anyone aware of a tool that I can use to check my Verilog
> code for undefined signals?  Preferrably, it will be available
> for my favorite price -- free.  I'm just worried that I might
> not catch all of the undefined signals during simulation.

> TIA,
> Mike Woodring
> SW/HW Engineer
> IRE

Mike,

        What you've found is a FEATURE, not a BUG.  Just for the
record, I think it's broken.  Never the less, it is legal.  The IEEE
1364 standard even has a section dedicated to this feature (3.5
Implicit declarations).  Here's the most pertinent information:

        "These implicitly declared nets shall be treated as scalar
         nets of type wire.  See Section 16 for a discussion of
         control of the type for implicitly declared nets with the
         `default_nettype compiler directive."

        Nuts, not only are they legal, there are compiler directives
to control them.  If that is defined, how come there isn't a compiler
directive that makes them illegal?!!!

                Monte

--
Monte Becker                                    Currently located at:
MSB Consulting Services                         Digital Equipment Corp
                                                Phone - 508 493 0231



Sun, 23 Jan 2000 03:00:00 GMT  
 
 [ 4 post ] 

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