wait statement question 
Author Message
 wait statement question

an example from my textbook:

This little model works fine - but if I comment out the
  wait (Reset !==1);
then the sim gets stuck in a loop. I checked out some docs on the wait
statement - they all say that the statement after the wait will get
executed when the condition becomes true (level driven not event) - but
why do we have to have the extra wait?

Thanks

Daniel

module dff_wait(D, Q, Clock, Reset);

output Q; input D, Clock, Reset; reg Q; wire D;

always begin
  wait (Reset == 1) Q=0;
  wait (Reset !==1);
  end

endmodule

--
==============================================

 Hardware Engineer, BRAS Group Platform Team
de Villermontstraat 38, 2550 Kontich, BELGIUM
   Tel: +32 3 450 3599 Fax: +32 3 450 3285
==============================================



Tue, 30 Dec 2003 23:39:49 GMT  
 wait statement question
First off, unless your textbook is trying to prove a point about sticking
the simulator I suggest you get a new one since that is the most god-awful
definition of a FF I've ever seen.  Of course, that's just my opinion.. :)

Now, as I understand it the reason that it gets stuck without the 2nd wait
is that once Reset goes high Q gets assigned, and the end statement is
reached.  As a  result execution goes back to the top, sees that Reset is
still high, does the assignment again, and repeats.  So simulation time
is never advanced since there is always something more to do in the
current time step.  The extra wait keeps that from happening since Reset
cannot simultaneously be 1 and not 1.

-Brian

Quote:

> an example from my textbook:

> This little model works fine - but if I comment out the
>   wait (Reset !==1);
> then the sim gets stuck in a loop. I checked out some docs on the wait
> statement - they all say that the statement after the wait will get
> executed when the condition becomes true (level driven not event) - but
> why do we have to have the extra wait?

> Thanks

> Daniel

> module dff_wait(D, Q, Clock, Reset);

> output Q; input D, Clock, Reset; reg Q; wire D;

> always begin
>   wait (Reset == 1) Q=0;
>   wait (Reset !==1);
>   end

> endmodule

> --
> ==============================================

>  Hardware Engineer, BRAS Group Platform Team
> de Villermontstraat 38, 2550 Kontich, BELGIUM
>    Tel: +32 3 450 3599 Fax: +32 3 450 3285
> ==============================================



Wed, 31 Dec 2003 01:28:55 GMT  
 
 [ 2 post ] 

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