Verilog/FPGA Express Synth Problem 
Author Message
 Verilog/FPGA Express Synth Problem

I am having a problem with FPGA Express (bundled with Xilinx Student
Edition) detecting my resets in my final project. Basically it doesn't.
Even though I specify 0x01 as the reset value, it makes them all reset.
Could someone please help me out? Thanks!

Code fragment....


        begin
            if (reset == 1)
                lfsr_reg <= 6'b 000001; // guarantee register doesn't
load all 0's on reset
            else
                if (load == 1) // loading takes precedence over shift
enable
                    lfsr_reg <= load_data;
                else if (enable == 1)
                    lfsr_reg <= { (lfsr_reg[5] ^ lfsr_reg[0]) ,
lfsr_reg[5:1] }; // shift right
        end

FPGA Express synthesis results....

===============================================================================

|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS
| ST |
===============================================================================

|       lfsr_reg_reg       | Flip-flop |   6   |  N  | ?  | ?  | ?  | ?
| ?  |
===============================================================================

lfsr_reg_reg<3>
---------------
    Async-reset: reset

lfsr_reg_reg<1>
---------------
    Async-reset: reset

lfsr_reg_reg<5>
---------------
    Async-reset: reset

lfsr_reg_reg<0>
---------------
    Async-reset: reset

lfsr_reg_reg<4>
---------------
    Async-reset: reset

lfsr_reg_reg<2>
---------------
    Async-reset: reset

--
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610

<Remove the XYZ. for valid address>



Sat, 26 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem
I would try removing the space between 6'b and 000001 in the reset
portion of your code.

Mark

Quote:

> Code fragment....


>         begin
>             if (reset == 1)
>                 lfsr_reg <= 6'b 000001; // guarantee register doesn't
> load all 0's on reset
>             else
>                 if (load == 1) // loading takes precedence over shift
> enable
>                     lfsr_reg <= load_data;
>                 else if (enable == 1)
>                     lfsr_reg <= { (lfsr_reg[5] ^ lfsr_reg[0]) ,
> lfsr_reg[5:1] }; // shift right
>         end



Sat, 26 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem

Quote:

> I would try removing the space between 6'b and 000001 in the reset
> portion of your code.

So would I, but I think it is a red herring.  Synplify gets it
right with or without the space.  And if the space _is_ a syntax
error, then it is inexcusable for FPGA Express to silently give
the wrong answer.  It's a nice small example: beat 'em up about it.
(But first, check that this code really is what you submitted to
the synthesis tool!!!)

BTW: When using LFSRs I like to add some logic to catch the all-zero
state and automatically jam one of the flipflops to 1.  This is
usually very cheap, and protects against the LFSR locking-up
if it happens to get pushed into the all-zero state by a supply
transient or other act of Beelzebub. And it would obviate your
need for reset to a non-zero value....

Quote:

> > Code fragment [slightly edited in the interests of conciseness]
> > [problem: lfsr_reg is reset to 000000 by FPGA Express's logic]

> >     begin
> >      if (reset == 1)        // guarantee not all 0's on reset
> >       lfsr_reg <= 6'b 000001;
> >      else if (load == 1)    // loading wins over shift enable
> >       lfsr_reg <= load_data;
> >      else if (enable == 1)  // shift right
> >       lfsr_reg <= { (lfsr_reg[5]^lfsr_reg[0]), lfsr_reg[5:1] };
> >     end

Jonathan Bromley


Sun, 27 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem
I am not a Verilog programmer, but looking at your code, I would guess
that the way it is written your reset is not an async reset, but rather
a sync reset. Perhaps the reset condition should be brought outside of
the clock domain? That is how it is done in VHDL.

It is clear that the reset state that is shown below is an async one. Do
you have any other example circuits where this works correctly?

Quote:

> I am having a problem with FPGA Express (bundled with Xilinx Student
> Edition) detecting my resets in my final project. Basically it doesn't.
> Even though I specify 0x01 as the reset value, it makes them all reset.
> Could someone please help me out? Thanks!

> Code fragment....


>         begin
>             if (reset == 1)
>                 lfsr_reg <= 6'b 000001; // guarantee register doesn't
> load all 0's on reset
>             else
>                 if (load == 1) // loading takes precedence over shift
> enable
>                     lfsr_reg <= load_data;
>                 else if (enable == 1)
>                     lfsr_reg <= { (lfsr_reg[5] ^ lfsr_reg[0]) ,
> lfsr_reg[5:1] }; // shift right
>         end

> FPGA Express synthesis results....

> ===============================================================================

> |      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS
> | ST |
> ===============================================================================

> |       lfsr_reg_reg       | Flip-flop |   6   |  N  | ?  | ?  | ?  | ?
> | ?  |
> ===============================================================================

> lfsr_reg_reg<3>
> ---------------
>     Async-reset: reset

> lfsr_reg_reg<1>
> ---------------
>     Async-reset: reset

> lfsr_reg_reg<5>
> ---------------
>     Async-reset: reset

> lfsr_reg_reg<0>
> ---------------
>     Async-reset: reset

> lfsr_reg_reg<4>
> ---------------
>     Async-reset: reset

> lfsr_reg_reg<2>
> ---------------
>     Async-reset: reset

> --
> Brian C. Boorman
> Harris RF Communications
> Rochester, NY 14610

> <Remove the XYZ. for valid address>

--

Rick Collins


remove the XY to email me.



Sun, 27 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem

Quote:

> I am not a Verilog programmer, but looking at your code, I would guess
> that the way it is written your reset is not an async reset, but rather
> a sync reset. Perhaps the reset condition should be brought outside of
> the clock domain? That is how it is done in VHDL.

Rick, the example is classic textbook Verilog for synthesis of an
async resettable register.  Synthesis tools recognise it and
infer the appropriate flipflop(s).  The always block (=process)
executes every time one of the "or"-ed signals in its sensitivity
list changes.  The qualifier "posedge" restricts the sensitivity
to only rising transitions of the qualified signal. "or" is a magic
operator for sensitivity lists and is not the same as logical OR.

These RTL constructs are effectively identical:

// _________________________________________Verilog


  if (rst) begin
    // asynch reset actions like q <= 0;
  end else begin  // or, perhaps, "end else if (enable) begin"
    // actions on rising clock edge like q <= d;
  end

--_____________________________________________VHDL

process (clk, rst)
begin
  if rst='1' then
    --asynch reset actions like q <= 0;
  elsif rising_edge(clk) then
    --actions on rising clock edge like q <= d;
  end if;
end process;

Aw, they even *look* about the same!  Putting both clk and rst
in the process sensitivity list is a clue to the synth tools
that they can use to infer a resettable FF, no?  And yes, I do know
that many VHDL programmers code their registers in a somewhat
different style, but most VHDL tools I've met will happily swallow
the process given above.

Jonathan Bromley

PS:  Am I right in thinking that the pattern hyphen/hyphen/space that
opens most VHDL comments is seen by newsreaders as the start of the .sig?
Or do the leading (indentation) spaces in the VHDL stop that being a
problem?



Sun, 27 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem
I see now Jonathan. I missed the reset showing in the sensitivity list.

Thanks for the help!

I know less about newsreaders and signatures than I do Verilog, so I
can't help you with that one.  ;^)

Quote:


> > I am not a Verilog programmer, but looking at your code, I would guess
> > that the way it is written your reset is not an async reset, but rather
> > a sync reset. Perhaps the reset condition should be brought outside of
> > the clock domain? That is how it is done in VHDL.

> Rick, the example is classic textbook Verilog for synthesis of an
> async resettable register.  Synthesis tools recognise it and
> infer the appropriate flipflop(s).  The always block (=process)
> executes every time one of the "or"-ed signals in its sensitivity
> list changes.  The qualifier "posedge" restricts the sensitivity
> to only rising transitions of the qualified signal. "or" is a magic
> operator for sensitivity lists and is not the same as logical OR.

> These RTL constructs are effectively identical:

> // _________________________________________Verilog


>   if (rst) begin
>     // asynch reset actions like q <= 0;
>   end else begin  // or, perhaps, "end else if (enable) begin"
>     // actions on rising clock edge like q <= d;
>   end

> --_____________________________________________VHDL

> process (clk, rst)
> begin
>   if rst='1' then
>     --asynch reset actions like q <= 0;
>   elsif rising_edge(clk) then
>     --actions on rising clock edge like q <= d;
>   end if;
> end process;

> Aw, they even *look* about the same!  Putting both clk and rst
> in the process sensitivity list is a clue to the synth tools
> that they can use to infer a resettable FF, no?  And yes, I do know
> that many VHDL programmers code their registers in a somewhat
> different style, but most VHDL tools I've met will happily swallow
> the process given above.

> Jonathan Bromley

> PS:  Am I right in thinking that the pattern hyphen/hyphen/space that
> opens most VHDL comments is seen by newsreaders as the start of the .sig?
> Or do the leading (indentation) spaces in the VHDL stop that being a
> problem?

--

Rick Collins


remove the XY to email me.



Sun, 27 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem
Brian,

From what you've given us this isn't necessarily a bug, since it is
possible the synthesizer inverted the sense of one of your register
bits.

Trace through the synthesized output, and/or perform
a structural simulation, to see if this is the case.
Maybe it clears the entire register, and then inverts the
bit you wants to set.

Steve



Mon, 28 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem

Quote:

> Rick, the example is classic textbook Verilog for synthesis of an
> async resettable register.  Synthesis tools recognise it and
> infer the appropriate flipflop(s).  The always block (=process)
> executes every time one of the "or"-ed signals in its sensitivity
> list changes.  The qualifier "posedge" restricts the sensitivity
> to only rising transitions of the qualified signal. "or" is a magic
> operator for sensitivity lists and is not the same as logical OR.

However, there is one slight discrepancy in Verilog for asynchronous SET
and RESET.


Which means that when RESET for instance becomes active (ie, switches to
1), a posedge is indeed detected and the flip-flop output is
asynchronously reset. This is correct.

But when both SET and RESET are active, say SET has priority over RESET
(so the output is 1), and then the SET signal becomes inactive.... your
output stays stuck at one, even though the only asynchronous signal is
the RESET.

That's a limitation of the Verilog RTL subset in my opinion. Not to
start a war here (please!) but the VHDL RTL style for flip-flops is much
more clean regarding that aspect. The Verilog RTL style is (IMHO) a
hack: you have to obey a specific order of nested IF conditions. Why? I
still didn't figure it out.

Do you find it normal to have a mismatch between pre and post-synthesis
simulation? I don't.

Alain.
--
-----------------------------------------------------------------------
 Alain RAYNAUD                                            META SYSTEMS
 R&D Logic Design Team                                          LP 853
                                   3 Avenue du Canada - Batiment Sigma
 Tel: (33) 01 64 86 61 69             91975 Courtaboeuf Cedex - FRANCE

-----------------------------------------------------------------------



Mon, 28 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem
Thanks everyone for comments/suggestions. I did figure out the problem, and yes,
FPGA Express did generate wrong logic. Even though what I wrote is legal Verilog
(is even in textbook I have), FPGA Express would not recognize proper reset unless
everything in the else... clause was bracketed by a begin....end.

Code fragment (with fixes)....


        begin
            if (reset == 1)
                lfsr_reg <= 6'b 000001; // guarantee register doesn't
                                        //load all 0's on reset
            else              begin // THIS ADDED                if (load == 1) //
loading takes precedence over shift
                    lfsr_reg <= load_data; // enable
                else if (enable == 1)
                    lfsr_reg <= { (lfsr_reg[5] ^ lfsr_reg[0]) ,
                                lfsr_reg[5:1] }; // shift right
              end // THIS ADDED
         end



Mon, 28 May 2001 03:00:00 GMT  
 Verilog/FPGA Express Synth Problem
<snip quoted intro-to-always-for-VHDL-codist>

Quote:
> However, there is one slight discrepancy in Verilog for asynchronous SET
> and RESET.

> Which means that when RESET for instance becomes active (ie, switches to
> 1), a posedge is indeed detected and the flip-flop output is
> asynchronously reset. This is correct.
> But when both SET and RESET are active, say SET has priority over RESET
> (so the output is 1), and then the SET signal becomes inactive.... your
> output stays stuck at one, even though the only asynchronous signal is
> the RESET.
> That's a limitation of the Verilog RTL subset in my opinion. Not to
> start a war here (please!) but the VHDL RTL style for flip-flops is much
> more clean regarding that aspect. The Verilog RTL style is (IMHO) a
> hack: you have to obey a specific order of nested IF conditions. Why? I
> still didn't figure it out.

I agree, although I have never hit this problem myself because I have
always used the "synchronous thought police" approach which says that
async (re)set is strictly for use at system initialisation, so my
designs have never used both in the same always block.

OTOH I would have hoped that the synthesis tool will notice that it
cannot synthesise hardware that will give the same results as
simulation; so it should grumble.  Synplify, to its shame, doesn't.

The hack, I suggest, comes from placing the "posedge" test within
the sensitivity list.  If you could use "posedge" as a genuine
operator, like VHDL's rising_edge() or 'EVENT, it would be OK:


 if (set)
   ...
 else if (reset)
   ...
 else if (posedge clk)
   ...

Much cleaner, and it would allow for such things as fancy flipflops
that can clock on either edge. This special-case behaviour of
posedge/negedge and the 'or' operator is one of many things about
Verilog that strike me as being only 0.8-baked. (Maybe some Verilog
guru will now pop up and tell me that the above example is correct
Verilog, in which case I apologise in advance!)

Quote:
> Do you find it normal to have a mismatch between pre and post-synthesis
> simulation? I don't.

Not only do I not find it normal, I find it offensive.  In practice,
of course, I cover myself by using only a "safe" synthesisable subset,
same as everyone else.  Thanks for alerting me to yet another
restriction on that subset.

Jonathan Bromley



Mon, 28 May 2001 03:00:00 GMT  
 
 [ 10 post ] 

 Relevant Pages 

1. ANNOUNCE: FPGA design with FPGA Express - UK Seminars

2. DLL of a Virtex FPGA and FPGA Express V3.3

3. ANNOUNCE: FPGA design with FPGA Express - UK Seminars

4. Problem with Tristate output in FPGA Express II...

5. Mixed Design Problem (FPGA Express/ACTEL)

6. For EDN Article -- Call For FPGA/Synth Benchmarks

7. For EDN Article -- Call For FPGA/Synth Benchmarks

8. For EDN Article -- Call For FPGA/Synth Benchmarks

9. FPGA design services in VHDL and Verilog, FPGA to ASIC conversion

10. Synth pb with verilog

11. FPGA Express

12. Synplicity vs Xilinx FPGA Express

 

 
Powered by phpBB® Forum Software