Are UDP and the case statement the same for combinational logic? 
Author Message
 Are UDP and the case statement the same for combinational logic?

Hi,
  Are UDP and case statement same for some combinational logic? What's
the difference between the following two implementation of MUX? Under
what condition should we use UDP? Under what condition should we use
case statement?
Peng

primitive prim_mux4to1 (DOUT, DIN3, DIN2, DIN1, DIN0, SEL1, SEL0);
  output DOUT;
  input DIN3, DIN2, DIN1, DIN0, SEL1, SEL0;

  table
    ???0 00 : 0;
    ???1 00 : 1;
    ??0? 01 : 0;
    ??1? 01 : 1;
    ?0?? 10 : 0;
    ?1?? 10 : 1;
    0??? 11 : 0;
    1??? 11 : 1;
  endtable  
endprimitive

module mux16to1 (DIN, SEL, DOUT);
  input [15:0] DIN;
  input [3:0] SEL;
  output DOUT;
  reg DOUT;


  begin: blk1
    case (SEL) // synopsys infer_mux
      4'b0000: DOUT <= DIN[0];
      4'b0001: DOUT <= DIN[1];
      4'b0010: DOUT <= DIN[2];
      4'b0011: DOUT <= DIN[3];
      4'b0100: DOUT <= DIN[4];
      4'b0101: DOUT <= DIN[5];
      4'b0110: DOUT <= DIN[6];
      4'b0111: DOUT <= DIN[7];
      4'b1000: DOUT <= DIN[8];
      4'b1001: DOUT <= DIN[9];
      4'b1010: DOUT <= DIN[10];
      4'b1011: DOUT <= DIN[11];
      4'b1100: DOUT <= DIN[12];
      4'b1101: DOUT <= DIN[13];
      4'b1110: DOUT <= DIN[14];
      4'b1111: DOUT <= DIN[15];
    endcase
  end
endmodule



Wed, 28 Dec 2005 11:00:23 GMT  
 Are UDP and the case statement the same for combinational logic?
Hi,
  Typically UDPs are used in Cell library models and NOT for
synthesis.
In UDP all possible combinations of inputs,where the o/p produces a
known value must be explicitly specified. For other unspecified
inputs, the output is x. Z is not allowed in UDP. It is treated as x.
  For more info. about UDP rules, refer some good book. (May be Samir
Panitkar).
   In case, for unspecified values you have to include default state.
In order to treat x, z you have to use casex and casez.

HTH,
Ajeetha

http://www.noveldv.com

Quote:

> Hi,
>   Are UDP and case statement same for some combinational logic? What's
> the difference between the following two implementation of MUX? Under
> what condition should we use UDP? Under what condition should we use
> case statement?
> Peng

> primitive prim_mux4to1 (DOUT, DIN3, DIN2, DIN1, DIN0, SEL1, SEL0);
>   output DOUT;
>   input DIN3, DIN2, DIN1, DIN0, SEL1, SEL0;

>   table
>     ???0 00 : 0;
>     ???1 00 : 1;
>     ??0? 01 : 0;
>     ??1? 01 : 1;
>     ?0?? 10 : 0;
>     ?1?? 10 : 1;
>     0??? 11 : 0;
>     1??? 11 : 1;
>   endtable  
> endprimitive

> module mux16to1 (DIN, SEL, DOUT);
>   input [15:0] DIN;
>   input [3:0] SEL;
>   output DOUT;
>   reg DOUT;


>   begin: blk1
>     case (SEL) // synopsys infer_mux
>       4'b0000: DOUT <= DIN[0];
>       4'b0001: DOUT <= DIN[1];
>       4'b0010: DOUT <= DIN[2];
>       4'b0011: DOUT <= DIN[3];
>       4'b0100: DOUT <= DIN[4];
>       4'b0101: DOUT <= DIN[5];
>       4'b0110: DOUT <= DIN[6];
>       4'b0111: DOUT <= DIN[7];
>       4'b1000: DOUT <= DIN[8];
>       4'b1001: DOUT <= DIN[9];
>       4'b1010: DOUT <= DIN[10];
>       4'b1011: DOUT <= DIN[11];
>       4'b1100: DOUT <= DIN[12];
>       4'b1101: DOUT <= DIN[13];
>       4'b1110: DOUT <= DIN[14];
>       4'b1111: DOUT <= DIN[15];
>     endcase
>   end
> endmodule



Sat, 31 Dec 2005 00:28:57 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. wire and reg and modelling of combinational logic

2. feed back of combinational logic.

3. How to eliminate glitches for combinational logic design

4. feedback input with combinational logic!

5. This week's Coding tip: modeling combinational logic with inertial delays

6. question on combinational logic synthesis for FPGA

7. Combinational logic and gate delays - Help

8. This week's Coding tip: modeling combinational logic with inertial delays

9. case statement flipflop statement

10. difference if statement with case statement?

11. Initial Statement within a UDP

12. I am looking labview driver for Tektronix TLA704 logic analyzer

 

 
Powered by phpBB® Forum Software