Verilog HDL (IEEE PAR 1364) Working Group Meeting 
Author Message
 Verilog HDL (IEEE PAR 1364) Working Group Meeting

This is to announce the kick off meeting of the Verilog HDL Working
Group. As most of you already know, the IEEE accepted PAR 1364 in June.
The goal of the project is have the Verilog HDL (including the PLI) accepted
as an IEEE standard.

The kick meeting is scheduled for

        Thursday, October 14, 1993
        1:00-5:00 PM
        Mentor Graphics, San Jose

I've included the general annoucement for the IEEE DASC Working Group
meetings below. It contains directions on how to get to Mentor Graphics
as well as the times of other DASC meetings for those interested.

As for the Verilog HDL meeting - the purpose of the meeting is to bring
interested participants up to date as to the status of Verilog HDL and
plan our course for the remaining work required to achieve standardization.

The meeting is open to all interested. Though this is a WORKing group meeting.
As the name implies, we will be looking for active participants who are
willing, and have the time, to get involved and sign up for part of the work
which remains. We will try to schedule a general update and information
session at the Verilog HDL Conference.

For those who are located on the East Coast and have problems
travelling to the West Coast, don't worry. Stay tuned to this news group
or contact me after the DASC meeting. There will be an avenue for your
participation as well.

If you have any questions, you can contact me through


Tel:    (613)-763-3202

... John

Included file .....

                   IEEE CS DASC WORKING GROUP MEETINGS
                           October 14-16, 1993
                             Mentor Graphics
                         1001 Ridder Park Drive
                              San Jose, CA

FINAL SCHEDULE !!!!!!

The DASC meetings will be held on Thursday October 14 through Saturday
October 16.  There will be no registration fee for the meeting,
however, as you may have heard, the DASC is going to a yearly
subscription of $150.00.  I will be collecting this for those who wish
to pay it.  For Government people, this is can be called a
registration fee.  It can be paid by cash, check, or Credit Card.

The formal DASC meetings will not start until 1:00 PM on Thursday so
that IEEE training can be given to DASC working group chairs.  This
training is available to anyone who wishes to attend, but is HIGHLY
RECOMMENDED for Working Group Chairs.  Meeting Schedules are listed
below:

Thursday October 14th

REGISTRATION FROM 8:00 AM

9:00am -12:00  IEEE Working Group Chair Training
               Mary Lynne Nielsen of IEEE Standards will provide
               training for Working Group Chairs and any other        
               interested party on the Standards Development process
               in the IEEE.  This training is HIGHLY RECOMMENDED for
               all working group chairs.    

VHDL Analysis And Standardization           1:00pm-5:00pm
Group - PAR 1076
Stan Krolikoski, Chair

Verilog Working Group                       1:00pm-5:00pm
PAR 1364
John Mancini, Chair

DASC Steering Committee Meeting             5:30-7:00pm

Friday, October 15

REGISTRATION 8:00am - 9:00am

Shared Variable Working Group   (25)        9:00am-5:00pm
PAR 1076a
Steve Bailey, Chair

VHDL Analog Extensions Working Group  (25)  9:00am-5:00pm
PAR 1076.1
Mark Brown, Chair

VHDL Utility Library Working Group  (15)    1:00pm-5:00pm
PAR 1076.5
Gabe Moretti

VHDL Standard Synthesis Package  (20)       9:00am-500pm
PAR 1076.3
Ken Scott, Chair

Math Package Working Group  (15)            9:00am-12:00pm
PAR 1076.2
Jose Torres, Chair

Saturday, October 16

VHDL Standard Timing Methodology  (35)      9:00am-5:00pm
PAR 1076.4
Victor Berman, Chair

Study Group on System Design    (15)        9:00 am-5:00pm
Language
David Barton, Chair

                        DIRECTIONS TO MENTOR GRAPHICS

Mentor is located at 1001 Ridder Park Drive.

From San Jose Airport:

Make a left out of Airport and turn right onto Airport Blvd.  Follow
Airport Blvd to North First St.  Turn Left on North First St to
Brokaw Rd.  Make a right turn on Brokaw Rd.  Take Brokaw to Ridder;
Turn left on Ridder Park Drive.  Mentor is on the Left.  

From San Francisco Airport:

Take Bayshore Freeway South, 101, toward San Jose.  After reaching
San Jose area, exit on to N First St.  Take N First St to Brokaw Rd.
Turn Right on Brokaw Rd.  Take Brokaw Rd to Ridder.  Left on
Ridder.  Mentor is on Left.    

                                                AREA HOTELS

RED LION HOTEL
2050 Gateway Place
San Jose, CA 95110
(408) 453-4000
(800) 547-8010

Radissin Plaza Hotel
1471 North Fourth St
San Jose, CA 95112
(408) 452-0200

The Beverly Heritage Hotel
1800 Barber Lane
Milpitas, CA 95035
(408) 432-6311

Hyatt Airport
1740 North First St
San Jose, CA 95112
(408) 993-1234

-------------
Giovanni (John) Mancini  Bell-Northern Research, Ltd    Ph.: (613) 763-3202
                         P.O. Box 3511, Station C        

                         K1Y 4H7  

disclaimer: I don't speak for my company, I don't own one.

"Vote early and vote often..." Maurice Duplesis



Tue, 19 Mar 1996 23:55:33 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. PAR 1364 (Verilog) Working Group Meeting Dec. 17

2. IEEE 1364 Working Group Minutes

3. IEEE 1364 Working Group Minutes - 12/17/93

4. Where can I find IEEE Par-1364?

5. IEEE 1364 Verilog PLI-TSC Request for Enhancements, Errata

6. Verilog 2001 (1364-2001 IEEE Standard) Question

7. Gate level primitives in IEEE 1364 Verilog standard...

8. delay_or_event_control construct in IEEE 1364 Verilog

9. IEEE 1364 and Verilog-A Courses in Feb in Silicon Valley

10. Verilog is now IEEE 1364 standard

11. IEEE 1364 Verilog PLI-TSC Request for Enhancements, Errata

12. Minutes of the 3rd IEEE Scheme Working Group meeting

 

 
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