VHDL & Verilog Compared and Contrasted 
Author Message
 VHDL & Verilog Compared and Contrasted

Reply to Gerard M Blair's request for the VHDL versus Verilog.

The first point to be aware of is that the choice between VHDL & Verilog is:

    * Dependent upon EDA (or other) tool availability
    * Based on personal preferences
    * Based on commercial, business and marketing issues

The choice is not based on the technical capability of the language,
practically everything modeled in one language can also be modeled
in the other. There very few exceptions.

I am presenting a tutorial paper at DAC on this very subject.

I have also written a book, to be published on June 1st, which
covers this very subject in much more detail. It is called:

                HDP Chip Design
  A Practical Guide for Designing, Synthesizing and
  Simulating ASICs and FPGAs using VHDL or Verilog

For more information see:
  http://www.*-*-*.com/ ~asmith



Sun, 01 Nov 1998 03:00:00 GMT  
 VHDL & Verilog Compared and Contrasted

Quote:

> Reply to Gerard M Blair's request for the VHDL versus Verilog.

> The first point to be aware of is that the choice between VHDL & Verilog is:

>     * Dependent upon EDA (or other) tool availability
>     * Based on personal preferences
>     * Based on commercial, business and marketing issues

> The choice is not based on the technical capability of the language,
> practically everything modeled in one language can also be modeled
> in the other. There very few exceptions.

The issue is not whether there are structures which can only be coded in
one language or another; the issue is efficiency in coding.  You can code
anything in machine-code that you can write in C or C++.  However, for
most applications C/C++ will be much more efficient.

So, I guess I'd have to disagree with your paper.  Everyone is concerned
about productivity these days, and if I read your posting right, you're
saying it's not an issue.

Regards,
Erik Jessen



Sat, 07 Nov 1998 03:00:00 GMT  
 
 [ 2 post ] 

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