COURSE: High Level Design Using Verilog, Nov 6-10, Beaverton OR 
Author Message
 COURSE: High Level Design Using Verilog, Nov 6-10, Beaverton OR

Qualis Design Corporation will be offering another session of its popular
course, `A Comprehensive Introduction to High Level Design Using Verilog' in
October.  Additional details are provided below.

------------------------------------------------------------------------------

          A Comprehensive Introduction to High Level Design
                            Using Verilog

                        November 6 - 10, 1995
                          Beaverton, Oregon

                             Presented by
                      Qualis Design Corporation

`A Comprehensive Introduction to High Level Design Using Verilog' is a
fast paced, 5-day hands-on, multimedia course designed not only to
teach High Level Design techniques and the Verilog language, but to
make class participants immediately productive in a system design
environment using state-of-the-art simulation and synthesis tools.

After an introduction to Verilog, the course deviates from the
traditional bottom-up, gates-to-behavi{*filter*}modeling presentation of
other Verilog courses and reverses the flow, teaching top-down design
practices, with early special emphasis on coding for synthesis,
efficient testbench generation and advanced design verification
techniques. These skills are reinforced throughout the week while
teaching Verilog from a top-down perspective.

The course labs accommodate the learning aptitudes of a wide range of
students with diverse design experiences. Each lab is structured into
three parts:

     1.        Fundamental Concepts Review and Experience
     2.        Recognition of Common Mistakes and Correcting Problems
     3.        Additional Material for Advanced Students

All students complete parts one and two of each lab.  Part three is
for students who finish early and want to learn additional material.
This lab structure caters to all student skill levels and provides
excellent opportunities to expand one's knowledge of Verilog
simulation and synthesis techniques.

Each day of class includes interactive lecture sessions with 2-4 labs
and written exercises distributed throughout the day.  Students will
have access to individual Sun Sparcstations, the Verilog simulation
environment, and the Synopsys DC Expert synthesis environment for use
during the laboratory sessions. The instructor presents the material
using a projection system that allows 30% more material to be
presented in a given amount of time with vivid, interest-grabbing
color slides, as compared to black & white overheads.

About Your Instructor
---------------------
`A Comprehensive Introduction to High Level Design Using Verilog' is
conducted by Cliff Cummings, Director of Training and Principal
Engineer at Qualis Design.  Mr. Cummings has completed many ASIC and
FPGA designs and system simulation projects, and is capable of
answering the very technical questions asked by experienced design
engineers.

Mr. Cummings is a principal member of the IEEE 1364 Verilog
Standardization committee and has taught dozens of Verilog classes and
advanced Verilog HDL seminars.  He has also presented eight papers on
topics including ASIC test vector generation, FPGA design
methodologies, Verilog passive device modeling, board test generation
techniques, and inter-tool flow for system simulation.  Two of Mr.
Cummings' works were voted Best Paper at the 1993 and 1994
International Cadence Users Conferences.

Mr. Cummings, who holds a BSEE from Brigham Young University and an
MSEE with Computer Science minor from Oregon State University, is a
member of the IEEE and the Eta Kappa Nu, Tau Beta Pi and Sigma Delta
Pi Honor Societies.

About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of High Level Design consulting and
training services.  The company provides services to leading-edge high
technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, Northern Telecom and Bell-Northern Research.

Qualis High Level Design Training Courses are conducted on leading-
edge Sun workstations using the latest EDA vendor tools, and are
taught by engineering professionals with extensive digital design
experience.  Engineers who complete the High Level Design With Verilog
course will be more efficient users of system simulation tools, will
be capable of implementing advanced simulation environments, and will
have the knowledge to successfully complete complex design projects.
Engineers with previous exposure to Verilog and VHDL will also benefit
from the leading-edge material presented.

Additional Information
----------------------
The High Level Design Using Verilog course is taught over five
consecutive days.  Complimentary continental breakfast, a full lunch
and afternoon refreshments are provided for each day of the class.
Lodging conveniently located near the class site is available, with
morning and evening shuttle service.

The next regularly scheduled class date is:

`A Comprehensive Introduction to High Level Design Using Verilog'

     Class Date:    November 6 - 10, 1995
     Time:          8:30 AM to 5:00 PM

     Class Location:
                    Qualis Design Corporation
                    Atrium Training Room
                    Beaverton, OR

For more information about this course, including course description
and syllabus, contact us at:

                      Qualis Design Corporation
                     15455 NW Greenbrier Parkway
                              Suite 250
                       Beaverton, OR 97006 USA

                        Phone: +1-503-531-0377
                         FAX: +1-503-629-5525

-------------------------------------------------------------------
Copyright (c) 1995 Qualis Design Corporation.  All rights reserved.

`DC Expert' is a trademark of Synopsys, Inc.
`Verilog' is a registered trademark of Cadence Design Systems, Inc.



Tue, 24 Mar 1998 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. COURSE: High Level Design Using Verilog, Nov 6-10, Beaverton OR

2. COURSE: High Level Design Using VHDL, Oct 30-Nov 3, Beaverton OR

3. COURSE: High Level Design Using VHDL, Oct 30-Nov 3, Beaverton OR

4. COURSE: High Level Design Using Verilog, Beaverton, Oregon

5. COURSE: High Level Design Using Verilog, Beaverton, Oregon

6. COURSES: High Level Design Using Verilog, Beaverton, Oregon

7. COURSES: High Level Design Using Verilog, Beaverton, OR

8. COURSE: High Level Design Using Verilog, March 25-29, Beaverton OR

9. COURSE: High Level Design Using Verilog, Feb 12-16, Beaverton OR

10. COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR

11. COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR

12. COURSE: High Level Design Using Verilog, Oct 9-13, Beaverton OR

 

 
Powered by phpBB® Forum Software