Archive-name: verilog-faq
Version $Id: verilog-faq,v 1.9 1994/03/26 23:27:08 sjp Exp sjp $
This is the FAQ (Frequently Asked Questions) list for the newsgroup
comp.lang.verilog. It is an attempt to gather in one place the answers
to common questions and to maintain an updated list of publications,
services, and products. Please read this document before posting.
This article is posted bi-weekly. It is also available from the
archive for this group.
If you haven't already done so, reading the posts on
news.announce.newusers titled "A Primer on How Work With the Usenet
Community", "Answers to Frequently Asked Questions about Usenet" and
"Hints on writing style for Usenet" would be a good idea. They are "a
guide to using it [Usenet] politely, effectively and efficiently."
Your comments, additions, and corrections to this list are welcome:
Subject: Table of Contents
From: P01
Legend: + new
- deleted
! changed
Preface
P01. Table of Contents
P02. Viewing this article
P03. Where to get the most recent version of this FAQ
P04. How does FTP work?
Introductory
I01. What is Verilog?
I02. Who's bright idea was this? (A short history)
I03. What is comp.lang.verilog?
I04. Is there an archive for this group?
General Topics
G01. Books and Reference material on Verilog
! G02. Verilog vendors and products
G03. Is there a verilog.el for GNU emacs?
G04. What is PLI?
G05. Is there a version that runs on a IBM PC clone?
G06. Is the a vgrind def file?
G07. Is there a free verilog parser available?
G08. Is there a free Verilog simulator?
Cadence Verilog-XL
C01. About Cadence
C02. What's the difference between +speedup, +caxl, and turbo?
Subject: Viewing this article
From: P02
To skip to a particular question numbered xxx, use "/xxx" with most
pagers. In GNU Emacs type "M-C-s xxx", (or C-r to search
backwards), followed by ESC to end the search.
To skip to new or changed questions, use "/^S.*[!+]" with most
pagers and "M-C-s ^S.*[!+]" in GNU Emacs.
This article is in digest format. Nn may have already broken this
message into separate articles; if not, then type "G %". In rn, use
^G to skip sections.
This article is treated as an outline when edited by GNU Emacs. Run
"M-x describe-mode" to see available outline-mode commands. Useful
commands are "C-c C-s" (show-subtree) and "M-x show-all"
Numbers in square brackets denote the month and year of the last
update.
Subject: Where to get the most recent version of this FAQ
From: P02
At this time, this document is not archived on the normal FAQ
archive sites. It is posted frequently to comp.lang.verilog.
Subject: How does FTP work?
From: P03
FTP is a way of copying files between networked computers. If you
need help in using or getting started with FTP, send e-mail to
with
send usenet/news.answers/ftp-list/faq
in the body.
Subject: What is Verilog?
From: I01
Verilog HDL is a hardware description language used to design and
document electronic systems. Verilog HDL allows designers to design
at various levels of abstraction. It is the most widely used HDL
with a user community of more than 15000 active designers.
Subject: Who's bright idea was this? (A short history)
From: I02
Verilog HDL originated circa 1983 at Gateway Design Automation,
which was then located in Acton, MA. The company was privately held
at that time by Dr. Prabhakar Goel, the inventor of the PODEM test
generation algorithm. Verilog HDL was designed by Phil Moorby, who
was later to become the Chief Designer for Verilog-XL and the first
Corporate Fellow at Cadence Design Systems.
Moorby built a simulator around Verilog-XL in 1984-85, and then went
on to make his second major contribution at GDA, viz. the XL
algorithm for every fast gate-level simulation, which was first
productized in 1986.
Gateway Design Automation grew rapidly with the success of
Verilog-XL and was finally acquired by Cadence Design Systems, San
Jose, CA in 1989. Up till this time, Verilog HDL was still a
proprietary language, being the property of Cadence Design Systems.
Cadence Design Systems decided to open the language to the public in
1990, and thus OVI was born.
Subject: What is comp.lang.verilog?
From: I03
[extracted from ftp.uu.net:/usenet/control/comp/comp.lang.verilog.Z]
comp.lang.verilog is an unmoderated newsgroup which passed its vote
for creation by 332:9 as reported in news.announce.newgroups on 12
Dec 1991.
For your newsgroups file:
comp.lang.verilog Discussing Verilog and PLI.
The charter, culled from the call for votes:
The USENET group is intended at providing a forum for the discussion
of topics specific to Verilog, PLI (programming language interface),
SDF (Standard delay file format), Synthesis guidelines, compliance
and Verilog modeling. It will also provide users with an ability to
share Verilog/PLI utilities. Users can also use the forum to discuss
any Verilog related issues proposed by Open Verilog International
and its organizational and technical committees.
Subject: Is there an archive for this group?
From: I04
Yes. Out of the goodness of our hearts, we here at Cray Research
provide an anonymous ftp archive for the postings to
comp.lang.verilog and related files and information. This archive is
read only; Cray does not allow non-employees to write into its file
systems. If you have something to contribute, send it to me
ftp.cray.com:/pub/comp.lang.verilog/
In addition, the University of Windsor maintains an archive of
postings to several of the CAD related newsgroups. One of these is
comp.lang.verilog:
ftp.cs.uwindsor.ca:/pub/local/vlsi/comp.lang.verilog/
Subject: Books and Reference material on Verilog - REF_FAQ v1b0
From: G01
Alphabetical listing of materials by category:
* New or revised since REF_FAQ v1a0
VERILOG REFERENCE MATERIALS
===========================
*(R3) "DIGITAL DESIGN AND SYNTHESIS WITH VERILOG HDL", by
E. Sternheim, R. Singh, Y. Trivedi, R. Madhavan and
W. Stapleton
(R2) "DIGITAL DESIGN WITH VERILOG HDL", by
E. Sternheim, R. Singh and Y. Trivedi
*(R7) "INSIDE HDL", by L. Saunders and Y. Trivedi, regular
column in ASIC & EDA Magazine
*(R4) "QUICK REFERENCE FOR VERILOG HDL", by
R. Madhavan
*(R6) "SUCCESSFUL ASIC DESIGN THE FIRST TIME THROUGH", by
J. Huber and M. Rosneck
(R1) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE", by
D. Thomas and P. Moorby
*(R5) "VERILOG HDL 2.0 LANGUAGE REFERENCE GUIDE", by
Sutherland HDL Consulting
OPEN VERILOG INTERNATIONAL (OVI) REFERENCE MATERIALS
====================================================
(O6) "1993 OVI DIRECTORY OF SUPPORT FOR VERILOG HDL"
*(O1) "LANGUAGE REFERENCE MANUAL" (LRM), Version 2.0
*(O7) "OPENEXCHANGE"
*(O8) "OPENEXCHANGE" (Back Issues)
(O4) "PROCEEDINGS FROM '92 OVI USER GROUP MEETING"
(O5) "PROCEEDINGS FROM '93 INT'L VERILOG HDL CONF."
*(O2) "PROGRAMMING LANGUAGE INTERFACE" (PLI), Version 2.0
*(O3) "STANDARD DELAY FILE FORMAT MANUAL" (SDF), Version 2.0
VENDOR REFERENCE MATERIALS
==========================
(V4) "CADENCE VERILOG TRAINING COURSE LABS & SOLUTIONS"
(V3) "CADENCE VERILOG-XL TRAINING COURSE"
(V2) "GRAPHICAL OUTPUT FOR THE VERILOG PRODUCT FAMILY REFERENCE"
*(V5) "VERILOG HDL TRAINING COURSE", by Sutherland HDL Consulting
*(V1) "VERILOG-XL REFERENCE MANUAL"
*REF_FAQ REFERENCE-INCLUSION POLICY
==================================
VERILOG REFERENCE MATERIALS
===========================
(R1) "THE VERILOG HARDWARE DESCRIPTION LANGUAGE", by D. Thomas
and P. Moorby.
ISBN 0-7923-9126-8
Kluwer Academic Publishing Co.
P.O. Box 358
Hingham, MA 02018
Phone: 617-871-6600
FAX: 617-871-6528
- Text examples are available upon e-mail request to
- My personal favorite. Good insights into the Verilog
language by P. Moorby, one of the original authors of
Verilog. (Submitted by Cliff Cummings)
(R2) "DIGITAL DESIGN WITH VERILOG HDL", by E. Sternheim, R. Singh
and Y. Trivedi.
ISBN 0-9627488-0-3
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., Bldg. A107, San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
Or Contact Raj Singh, Phone: 408-749-8775, FAX: 408-749-8823
- Comes with a DOS-format floppy disk which includes all text
examples.
- Only complaint is that the book has no index.
- Y. Trivedi has a regular column in ASIC & EDA magazine.
(Submitted by Cliff Cummings)
(R3) "DIGITAL DESIGN AND SYNTHESIS WITH VERILOG HDL", by E. Sternheim,
R. Singh, Y. Trivedi, R. Madhavan and W. Stapleton.
ISBN 0-9627488-2-X
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
Or Contact Raj Singh, Phone: 408-749-8775, FAX: 408-749-8823
- Revised edition of (R2) with added 75 page Synthesis
chapter, 60-page Verilog HDL semantics chapter, and can
be purchased with a PC Verilog Simulator.
- This book DOES have an index.
- PC Simulator: "This is a full Verilog simulator with the
following exceptions: no PLI, specify blocks are ignored,
no switch level constructs but gates and primitives are
supported. Also there is a size limitation on the design."
(from Eli Sternheim).
(R4) "QUICK REFERENCE FOR VERILOG HDL", by R. Madhavan
ISBN 0-9627488-4-6 - 1993
Automata Publishing Company,
1072 S. Saratoga-Sunnyvale Rd., #A107, San Jose, CA 95129
Phone: 408-255-0705
FAX: 408-253-7916
Or Contact Raj Singh, Phone: 408-749-8775, FAX: 408-749-8823
Automata Verilog Quick Reference
================================
Advantages: - 24 pages - Spiral Bound.
- Intended to provide a quick reference for
semantics and examples.
- 3-page section on Synthesis supported/unsupported
constructs.
Disadvantages: - 24 Table of Content entries. No index.
- Synthesis section reportedly differs from the OVI
synthesis guidelines.
- Lists Net data types but not all of the Reg data
types, pp 2-3.
- Missing keywords: casex, casez, edge, endspecify,
macromodule, strength, xnor, xor, pg 4.
- Only lists 4 compiler directives, omits `timescale
(among others), pp 3-4
- Lists only three $system tasks ($time, $finish,
$setuphold scattered throughout examples).
- Typo: Combinational 3:1 MUX UDP example mis-labeled
as "inverted out", pg 7.
- Other minor omissions.
Recommendation: The Quick Reference would be enhanced by a
fine-print keyword and key-topic index inside the back cover.
(Note from Rajeev Madhavan: many of the above issues will be
addressed in the pending next revision)
(Submitted by Cliff Cummings)
(R5) "VERILOG HDL 2.0 LANGUAGE REFERENCE GUIDE", by Sutherland HDL
Consulting - Sept 1993
Sutherland HDL Consulting, 2417 Redwood Ct.
Longmont, CO 80503
Phone: 303-682-8864
FAX: 303-682-8864 (same number)
Sutherland Verilog Quick Reference
==================================
Advantages: - 24 pages.
- Intended to be a quick reference language
syntax guide.
- Lists 16 compiler directives including `timescale.
- Lists ~25 $system tasks, including 7
specify-block timing checks, $monitor,
$display, $stop, file-I/O tasks.
- Based on March 1993 - OVI 2.0 Spec (includes
some newer Verilog constructs)
Disadvantages: - 42 Table of Content entries. No index.
- No Synthesis section (but not necessarily
useful to, or needed by all Verilog users).
- Typo: Last Continuous Assignment Example at the
bottom of pg 16 lists [size] before (strength).
- Typo: `reset_all should be `resetall, pg 23.
Recommendation: The Quick Reference would be enhanced by a
fine-print keyword and key-topic index inside the back cover.
(Note from Stuart Sutherland: The typos will be corrected in
the pending next revision)
(Submitted by Cliff Cummings)
(R6) "SUCCESSFUL ASIC DESIGN THE FIRST TIME THROUGH", by
J. Huber and M. Rosneck.
ISBN 0-442-00312-9
Van Nostrand Reinhold
(publisher address?)
(The material in this book is) not limited to Verilog, but
it does give a good, practical introduction to the processes
and tradeoffs involved in designing an ASIC. (Submitted by
Daniel Sears)
(R7) "INSIDE HDL", by L. Saunders and Y. Trivedi, regular column
in ASIC & EDA Magazine
ASIC & EDA Magazine,
5150 El Camino Real Ste A31,
Los Altos, CA 94022-9873
Free subscription for qualified readers:
To qualify by phone: (800) 878-ASIC (2742)
Interactive online subscription number: telnet asic.com 2110
Monthly (occasionally missed) column covering Verilog and
VHDL modeling topics. Well worth reading. (Submitted by Cliff
Cummings)
OPEN VERILOG INTERNATIONAL (OVI) REFERENCE MATERIALS
====================================================
OVI is the organization charged with Verilog standardization
and language enhancements. OVI is currently pursuing Verilog
IEEE and ISO standardization.
For the following publications contact Lynn Horobin at the
OVI office.
Open Verilog International
Lynn Horobin
15466 Los Gatos Blvd., Suite 109-071
Los Gatos, CA 95032
Phone: (408) 353-8899 -- FAX: (408) 353-8869
(O1) "LANGUAGE REFERENCE MANUAL" (LRM), Version 2.0*
- $50 per copy, plus local sales tax
(O2) "PROGRAMMING LANGUAGE INTERFACE" (PLI), Version 2.0*
- $75 per copy, plus local sales tax
(O3) "STANDARD DELAY FILE FORMAT MANUAL" (SDF), Version 2.0*
- $50 per copy, plus local sales tax
(O4) "PROCEEDINGS FROM '92 OVI USER GROUP MEETING",
- $40 per copy, plus local sales tax
(O5) "PROCEEDINGS FROM '93 INT'L VERILOG HDL CONF.",
- $40 per copy, plus local sales tax
(O6) "1993 OVI DIRECTORY OF SUPPORT FOR VERILOG HDL",
- No charge
(O7) "OPENEXCHANGE", monthly OVI publication,
- No charge
(O8) "OPENEXCHANGE" (Back Issues), monthly OVI publication,
- $5 per copy
* Versions 1.0 of the LRM, PLI and SDF are still available.
VENDOR REFERENCE MATERIALS
==========================
(V1) "VERILOG-XL REFERENCE MANUAL", 3 Volumes, Version 1.6c June
1993 (Contact your local Cadence sales office)
- A good set of reference manuals with examples, after you
have learned Verilog, or if you have a specific question.
(Submitted by Cliff Cummings)
(V2) "GRAPHICAL OUTPUT FOR THE VERILOG PRODUCT FAMILY REFERENCE
MANUAL", Version 1.1f September 1989, Version 1.1f September
1989 Release notes, Version 1.2b November 1990 Release notes.
(Contact your local Cadence sales office)
- Explains the commands that are used with the GR_WAVES graphics
package. (Submitted by Cliff Cummings)
(V3) "CADENCE VERILOG-XL TRAINING COURSE", Version 3.3, August 1991.
(Contact your local Cadence sales office)
- Reasonable training materials.
- A number of the training slides contain examples with minor
syntax errors and other examples that must be corrected before
they will run (it is obvious that not all of the training
examples were tested).
- The training course notebook does not have an index and really
needs one. (Submitted by Cliff Cummings)
(V4) "CADENCE VERILOG TRAINING COURSE LABS & SOLUTIONS", Release 3.3.a
April 14, 1992. (Contact your local Cadence sales office)
- No index, but a good set of labs to accompany the training
course. (Submitted by Cliff Cummings)
(V5) "VERILOG HDL TRAINING COURSE", by Sutherland HDL Consulting
Sutherland HDL Consulting, 2417 Redwood Ct.
Longmont, CO 80503
Phone: 303-682-8864
FAX: 303-682-8864 (same number)
REF_FAQ REFERENCE-INCLUSION POLICY
==================================
If anyone is aware of other Verilog reference materials, please
forward the information to Cliff Cummings -
REF_FAQ Reference-Inclusion Policy:
(1) Materials should be released and publicly available
(pre-release announcements will no longer be included in
REF_FAQ).
(2) Publisher/Vendor pricing information will be added only upon
Publisher/Vendor request (exception: OVI published prices
have been noted).
(3) Reviews, if added, will be credited to the reviewer.
(4) Magazines will only be listed if they carry a regular
Verilog-related column (such as ASIC & EDA (R7)).
(5) These policies are subject to suggestions and change!
Subject: Verilog vendors and products
From: G02
Caveat: Many of these product descriptions were written by the
vendor. They may contain hype.
======================================================================
Vendor: Attest Software Inc.
4677 Old Ironsides Drive, Suite 100
Santa Clara CA 95054
Phone: (408) 982-0244
FAX: (408) 982-0248
Product: TDX (R)
Description: TDX is a high-performance, interactive fault simulation
and automatic test generation software system for Verilog.
The software is built around a high-performance concurrent
fault simulator that supports all of the unidirectional
primitives, wire types, and gate/net delays defined in the
Verilog 2.0 LRM. UDPs are also supported, along with
optimized built-in models for single and multi-port RAMs.
It is not necessary to sacrifice accuracy for fast fault
simulation.
The software supports the detailed pin timing and strobing
features found on "tester-per-pin" ATE.
TDX_FSIM - highly accurate, fast fault simulator with full
timing and states/strengths.
TDX_IDDQ - flexible, programmable transistor-short fault
simulation and vector selection for current measurement
testing.
TDX_STEP (TM) - static and dynamic testability analysis,
and test improvement program that supports both scan and
non-scan designs.
TDX_ATG - sequential test generation for scan and non-scan
designs. Tightly integrated with tdx_fsim, tdx_step, and
tdx_iddq.
Free demo executables are available by anonymous ftp from
netcom.netcom.com in /pub/attest. The demo software runs
on any small circuit, and also on an 8085 microprocessor
clone model that is available at the ftp site.
Supports: Sun Sparc, HP PA-RISC, and Windows NT.
======================================================================
Vendor: CAD Artisans, Inc.
2210 Meyers Ave.
Escondido, CA 92029
Phone: (619) 739-1845
Fax: ?
email: ?
Product: Ausim
Description: Ausim is a logic simulator. It has a translator to
translate Verilog into Ausim.
Supports: Sun, ?
======================================================================
Vendor: Cadence Design Systems, Inc.
555 River Oaks Parkway
San Jose, CA 95134
Phone: (408) 943-1234
Fax: (408) 943-0513
email: ?
Product: Verilog-XL
Description: The industry standard Verilog simulator.
Supports: most workstations
======================================================================
Vendor: Caesium Inc.
3542 Earl Drive
Santa Clara, CA 95051
Phone: (408) 248 4603
Fax: ?
Product: Verilog HDL Model Libraries
Description: Caesium Inc. provides Verilog HDL Model Libraries.
Features Include:
-----------------
1. Full Function.
2. Accurate Timing.
3. Synthesizable.
4. Intelligent X-handling.
5. Verilog HDL Source Code models.
6. Fast Execution.
7. Low Cost.
PRICE LIST
----------
Single User (PC plateform) and Educational discount pricing:
LSTTL models .............................. $250
ALSTTL models .............................. $250
ASTTL models .............................. $250
ACTTTL models .............................. $250
BCTTTL models .............................. $250
HCTTL models .............................. $250
FTTL models .............................. $250
STTL models .............................. $250
Corporate Site license is $750 per set listed above.
----------------------------------------------------
Memory and PAL model libraries are under development.
Please inquire about availability for your model needs.
Partial Function or Bus Function Models can be developed
at a nominal cost.
Supports: ?
======================================================================
Vendor: Chronologic Simulation
5150 El Camino Real
Los Altos, CA 94022
Phone: (800) VERILOG or (415) 965-3312
FAX: (415) 965-2705
Product: VCS, Verilog Compiled Simulator
Description: Product is a Verilog Compiler offering 10x speed
improvement on behavioural code, and 1/10 memory
usage; all as compared to Verilog-XL 1.6. Supports the
complete language, as well as interactive debugging.
Your mileage may differ.
Supports: Sparc SunOS, Sparc Solaris, HP PA-RISC, SGI and NeXT
------------
Product: VMC, Verilog Model Compiler
Description: Product takes Verilog HDL source models and compiles
them to C object modules for use with VCS, Verilog-XL
and other Verilog & VHDL simulators. Allows component
builders to release high performance, low memory,
proprietary models to their customers - as object form
- ie providing a very attractive alternative to source
protection/encryption.
Supports: Sparc SunOS, Sparc Solaris, HP PA-RISC
======================================================================
Vendor: Fintronic USA, Inc.
1360 Willow Road, Suite 205
Menlo Park, CA 94025
Phone: (415) 325-4474
FAX: (415) 578-0260
Product: FinSim Verilog Simulation Environment
Description: FinSim Verilog Simulation Environment is a complete
compiled simulation system for Verilog. It features
full language implementation including PLI 1.0, VCD,
and SDF(available in Dec '93).
FinSim utilizes a very fast Verilog analyzer with
extensive error checking mechanism. Simulation speed
is up to 50x faster than Verilog-XL for behavior-level
designs.
FinSim Verilog simulator supports VCD waveform display
tools from Veritools, Design Acceleration and Systems
Science. Schematic capture system is supported in Data
I/O ECS system.
Supports: Sun, Dec, SGI, Intel X86 under Windows NT, Unixware,
Interactive Unix
======================================================================
Vendor: i-Logix Inc.
22 Third Avenue
Burlington, MA 01803
Phone: (617) 272-8090
FAX: (617) 272-8035
Product: ExpressV-HDL
Description: Provides a graphical environment to develope
Statecharts. Equivalent Verilog or VHDL is
automagically generated.
Supports: ?
======================================================================
Vendor: Intergraph Electronics
Huntsville, Al 35894-0001
Phone: (205) 730-8543
FAX : (205) 730-8344
Product: VeriBest Design System
Description: The VeriBest suite of products provides an easy to use
ASIC/FPGA design environment. The environment will be
sold in a software only form as the VeriBest Designer
and will be bundled with Intergraph's TD1 hardware
platform as the VeriBest Design System. VeriBest
Designer has the following software components:
Electronics Desktop Manager - Our electronics specific
graphical desktop which organizes design data and
launches applications. The Electronics Desktop manager
includes the Design Methodology Manager, a tool that
allows software products to be organized into an
enforced process oriented flow (e.g., the steps
required to build an ASIC or FPGA as specified by a
silicon vendor).
ACEPlus Design Entry System - Our front-end design
entry editor that utilizes hierarchical design to
organize the use of primitive symbols and
representative blocks for Verilog source files or
State diagrams.
ACEPlus Designer - Our automatic HDL generator that
takes schematics and state diagrams created with
ACEPlus Design Entry System and automatically
generates simulatable VHDL, Verilog HDL, or ABEL HDL.
VeriBest Simulator - Our high performance, high
capacity Verilog-XL compatible simulator which
includes VeriScope, our graphical waveform viewer and
simulation controller.
Support: Sun Sparc, Intel 486 & Pentium
======================================================================
Vendor: interHDL, Inc.
1270 Oakmead Parkway, Suite 208
Sunnyvale, CA 94086
Phone: (408) 749-8775
Fax: (408) 749-8823
Product Name: Verifront, Veriframe, Verilint, interFlat
Description: interHDL develops and sells Verilog related tools for
the Verilog design community.
Verifront - Reads a Verilog HDL design, builds an
internal database and provides a set of database
access functions for developing in-house EDA
tools. This tool supports full set of the Verilog
language.
Veriframe - A graphical user interface for
managing Verilog HDL designs and for running
interHDL's EDA tools. It supports design hierarchy
browser, text editor, estimators, and other useful
utilities for Verilog designers.
Verilint - A syntax, semantic, and synthesis
rules checker for Verilog designs. It has its own
graphical user interface and a text editor. The tool
allows designers to interactively find and fix design
errors prior to simulation and synthesis.
interFlat - Reads hierarchical Verilog netlists,
flattens the hierarchy and writes a flat Verilog,
VHDL, EDIF, or FutureNet file. The operation of
flattening is extremely fast. Available also in source
code.
Supports: Sun, HP, RS6000, Alpha.
======================================================================
Vendor: Precedence Incorporated
4675 Stevens Creek Blvd., Suite 250
Santa Clara, CA 95051
Tel: (408) 345-4880
Fax: (408) 345-4884
email: ?
Product: SimMatrix co-simulation products:
Cadence Verilog / Vantage Spreadsheet Co-simulation
Cadence Verilog / Quickturn hardware emulator Co-simulation
Cadence Verilog / EPIC Design TimeMill and PowerMill Co-sim
Cadence Verilog / Mentor Lsim Co-simulation
Cadence Verilog / Silvaco SmartSpice Co-simulation
Mentor Graphics Quicksim II / Cadence Verilog-XL
Viewlogic Viewsim - VHDL / Cadence Verilog-XL
Description: Precedence co-simulation products allow designers to
simulate using both Verilog-XL and the specialized
design verification tools as shown above,
simultaneously and transparently. This is useful for
IC, ASIC and PCB simulation which includes blocks or
models in a variety of simulators and/or languages. At
the heart of this integrated simulation environment is
Precedence's extensible SimMatrix simulation backplane.
Supports: Sun, HP, other workstations
======================================================================
Vendor: Silicon Automation Systems, Inc.
1630 Oakland Road, Suite A-103
San Jose, CA 95131
Phone: (408) 437-9161
FAX: (408) 437-9040
email: ?
Product: V/X-SIM
Description: OVI compliant Verilog simulator. Includes source
de{*filter*}, hierarchy browser, and graphical waveform
display.
Supports: ?
======================================================================
Vendor: Simucad
32970 Alvarado-Niles Road
Union City, CA 94587
Phone: (510) 487-9700
Fax: (510) 487-9721
email: ?
Product: Silos III
Description: Silos III is the next generation of Simucad's Silos
simulator which was first introduced in 1983. It is an
integrated logic and fault simulation environment.
Silos III used Verilog to support top-down
methodology.
Supports: Sun, VAX, HP, RS6000, MIPS, PC
======================================================================
Vendor: Synopsys Inc.
700 East Middlefield Road
Mountain View, CA 94043
Phone: (415) 962-5000
Fax: (415) 965-8637
Product: HDL Compiler(tm) for Verilog
Description: The HDL Compiler family provides translation and
architectural optimization of Verilog design
descriptions prior to logic synthesis. It's
architectural optimization is based on resource
selection and implementation of DesignWare(tm)
Synthetic Designs. The HDL Compiler family works with
the industry-leading logic synthesis and test
synthesis product lines, Design Compiler(tm) and Test
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============================================================================
Subject: Is there a verilog.el for GNU emacs?
From: G03
The archives contain no less than three verilog modes for emacs:
1. ftp.cray.com:/pub/comp.lang.verilog/verilog.el.Z
Rick Eversole at Cadence maintains a verilog mode and
occasionally posts it to comp.lang.verilog. At this time it
supports only FSF 18.xx and Epoch. FSF 19.xx and Lucid Emacs
(lemacs) are not supported. It is available at the archive
if you have missed the posting and can not get it from the
archive of comp.lang.verilog.
2. ftp.cray.com:/pub/comp.lang.verilog/verilog-mode.Z
This one was written by Michael McNamara
3. ftp.cray.com:/pub/comp.lang.verilog/vlog-mode.tar.Z
and was also grabbed from a posting.
In addition, Cadence is now shipping an LSE (Language Sensitive
Editor) that appears to consist of Lucid Emacs with a set of elisp
files to implement the verilog mode.
Subject: What is PLI?
From: G04
PLI stands for Programming Language Interface. The PLI consists of
an interface mechanism, a set of routines to interact with the
simulation environment, and a set of routines to access the Verilog
internal data structures. These allow user supplied C code to
interact dynamically with the simulation and data structures.
Subject: Is there a version that runs on a IBM PC clone?
From: G05
See section G02: Verilog vendors and products
Subject: Is the a vgrind def file?
From: G06
Yes. Available in the archives. See section I04: Is there an
archive for this group?
Subject: Is there a free verilog parser available?
From: G07
Yes. There are two known public domain parsers.
There is one in the archive donated by Frank Bennett
hdl.y below is a verilog parser written using the Unix utility -
yacc. It by no means is a complete verilog parser. This only
represents a few nights of effort in front of the ole PC. This is
donated in the hope that this will enable additional work by
individuals interested in learning verilog & yacc.
Available in the archive as:
ftp.cray.com:/pub/comp.lang.verilog/hdl.y.Z
what he had to say about it:
I ran across a verilog-HDL parser authored by
ic.berkeley.edu in directory /pub/stcheng/vl2mv.tar.Z. It is part
of a verilog->bliff translator. It comes complete with a wrapper
for the translator, and contains the parser and code to build the
parse tree. One of the handiest things is a traverse routine
which echoes the input file back to the output by traversing the
data structures, thus giving you a template to base your own
application on.
The parser itself seems to contain most of the verilog-HDL
grammar, though many behavi{*filter*}constructs are unimplemented in
the data structure routines. It is still under development, so
there are bugs. I spent a few days hacking the code and removed a
lot of hooks to berkeley OCTTOOLS code that wasn't included with
the distribution. The code as I downloaded it didn't compile.
I'll place this on the anonymous FTP site here (ftp.eecs.umich.edu
in people/riepe) - you'll get a version that compiles (at least it
does on my decstation) and a list of bug fixes that have been sent
to me other people I've given it to.
This parser is also available in the archives as:
ftp.cray.com:/pub/comp.lang.verilog/verilog_parser.tar.Z
Subject: Is there a free Verilog simulator?
From: G08
No.
Subject: About Cadence
From: C01
Cadence Design Systems is one of the largest, if not the largest,
CAD vendors in the market. Until handing it over to OVI, Cadence
owned the Verilog language. Until recently, Cadence had the only
verilog simulator on the market: Verilog-XL. This is still the
industry standard.
Subject: What's the difference between +speedup, +caxl, and turbo?
From: C02
My name is Asad Khan, and I am a member of the Verilog-XL R&D team
at Cadence Design Systems. I wanted to take this opportunity and
clarify the situation vis-a-vis Turbo and +speedups option in
Verilog-XL, a subject of many recent postings.
The best way I can think of doing this is via a Q&A format, that
reflects some of the actual questions raised on this group :
Q. What is the +speedups option ?
The +speedups command-line option invokes a prototype new behavioral/RTL
engine in Verilog-XL that promises higher performance, with nominal
increased memory usage (averaging 10% of the total design size). This
engine has been in development since 1991 and existed as an option in
versions 1.6a.7 and 1.6b of Verilog-XL (with increasing levels of
performance and quality).
Q. What is -a ?
-a is the command-line option in Verilog-XL that invokes the XL gate-level
algorithm for high performance gate-level simulation. This algorithm ONLY
addresses gates and unidirectional transistors in a Verilog design, and
thus can be thought of as the "companion" of the new +speedups engine.
This has existed in a productized form in Verilog-XL since 1985.
Q. Why is performance via +speedups an option and why is it simply
not provided as default ?
(There is another broader question on why are there so many performance
options causing the user headaches, which is addressed later)
The new behavioral/RTL engine was under development all through 1992 and
early 1993. As such, we were simulataneously working on increasing its
performance, and removing the various and sundry bugs that new development
always has. We did not want our customers to be affected by the lower
quality on this new engine, compared to the default old engine, which has
been thoroughly tested in the field over a number of years.
Through late 1992 and early 1993, selected customers have been cooperating
with us in an extended Beta program in testing this new engine, and we
intend to productize it as "Verilog-XL Turbo", a new Cadence product.
Q. What is "Verilog-XL Turbo" ?
This is a new product that will be introduced in Q3'93. All behavi{*filter*}
performance enhancements implemented by Cadence up till that time will be
included along with other product enhancements. The +speedups improvements
will continue to be offered in the Verilog-XL product.
The Turbo product is undergoing beta-testing for performance and quality
through Q2'93.
Q. Does +speedups have limitations ? Does Turbo have limitations ?
(viz. will some features not work ? will the results be different ?)
+speedups, being a subset of the final Turbo product, had many limitations
that were being worked on in 1992. These are mentioned in the release
notes of Verilog-XL 1.6b etc. and were even posted by a customer on
comp.lang.verilog. ALL OF THESE WERE DUE TO THE FACT THAT +speedups
WAS UNDER DEVELOPMENT and was not productized. Thus the person who saw
differences in results by using +speedups was observing a bug with the
+speedups option, NOT expected usage. I wish he/she would send Cadence
(or myself) the testcase so we can assure that that problem will not
exist in upcoming Verilog-XL releases (i.e. Verilog-XL 1.7, ...)
ALL restrictions have been removed in Verilog-XL Turbo, and result
compatibility is assured. If there is a mismatch in results between
Turbo and non-Turbo versions of Verilog-XL, ONE OF THEM has a bug,
which Cadence would be eager to fix.
Q. What performance level can I expect with +speedups ? With Turbo ?
On designs that DO NOT contain any gates, transistors, path delays,
timing-checks or PLI, +speedups was observed to average around 2-2.5X
over Verilog-XL 1.6a. The performance improvement gets "diluted" when
the constructs/capabilities mentioned above are introduced into the
design simply because the new algorithm only speeds up behavioral/RTL,
even though all the other Verilog-XL capabilities are transparently
supported.
The Turbo evolution of +speedups has many more improvements and fixes
and has been observed on pure behavioral/RTL circuits to yield much higher
performance. Customer references will soon be available on actual numbers
observed, but 5X and 7X have been seen at customer sites on their
benchmarks.
Again, designs that contain non-behavi{*filter*}constructs like path delays,
transistors etc. are fully transparently supported, but the performance
applies only to the pure behavi{*filter*}level.
IF YOU ARE INTERESTED IN TESTING TURBO YOURSELF, AND VERIFYING THE
PERFORMANCE IMPROVEMENTS THAT TURBO YIELDS OVER 1.6A AND +SPEEDUPS
PLEASE HAVE SOMEBODY FROM YOUR COMPANY CONTACT THE PRODUCT MARKETING
MANAGERS FOR VERILOG LISTED BELOW :
Q. What is +caxl ? Why do I have to worry about so many performance options
and why can't the simulator simply take care of it for me ?
I will defer the +caxl question until a bit later, because that is a topic
worthy unto itself.
In general, inspite of being a tool vendor, I ABSOLUTELY agree that the
user should have to worry about as few options as possible, with the
tool providing the best performance by default.
I have given an explanation for the +speedups being an option in an earlier
answer, so that will be taken care of by Q3'93. -a being an option is
also being worked on, and will also be addressed in 1993 by Cadence.
However, +caxl will STILL remain an option, and there might be other
options in the future that might be of the same kind. Let me illustrate
the problem by explaining the motivation for +caxl.
CAXL is special algorithm designed to accelerate major classes of
continuous assignments by synthesizing them into gates and simulating
them using the XL gate-level algorithm. By the nature of the CAXL
algorithm, it has to be used carefully, because :
- it does NOT always yield increased performance
If the synthesized gate description is much more complicated than the
original continuous assignment, than clearly simulating it will be
more time-consuming than the CA. Think about a, b, c and d being 32-bit
wires, and the continuous assignment
d = (a === 2716) ? (b | c) ^ a : (~a & b) ^ c;
The 32-bit operations in the above CA (bitwise-or, and, comparison, xor)
are either single-cycle machine operations, or take very few machine
cycles while the gate level implementation of the above continuous
assignment will probably consist of hundreds of gates that would need many
hundreds of operations to compute.
But there is a large class of CA's that CAXL does EXTREMELY well on,
say around 10X performance. Single bit continuous assignments involving
logical/boolean operators are example of such continuous assignments.
So, the general idea is that CAXL can give a large performance boost when :
- a design has a large number of continuous assignments
- a majority of these CA's operate on smaller vector
widths (say <= 4).
So then, why can't the simulator itself make the decision (based on
heuristics etc.) about which continuous assignments to apply CAXL
on ? The following section goes a long way towards explaining this.
- it does NOT assure 100% result compatibility
The reasons all originate from the fundamental basis of the algorithm,
viz. using synthesized gates to achieve performance over continuous
assignments e.g. glitch behavior could differ between the CA and a
gate level implementation of it etc.
The above two issues seem to indicate that the choice to use CAXL or
not should be left to the user. There are some users who can derive
benefit from it, while others might not.
--
Steve Phillips Phone: (715) 726-5412
Cray Research, Inc. FAX: (715) 726-4345
Chippewa Falls, WI 54729
FAQ: Comp.lang.verilog Frequently Asked Questions (with answers)