How to eliminate glitches for combinational logic design 
Author Message
 How to eliminate glitches for combinational logic design

Can anybody here give me some general ideas how to eliminate glitches
for combinational logic design?  Or where can I find this kind of
knowledge?

Thanks a lot,
mingwei



Sat, 31 Jan 2004 10:02:38 GMT  
 How to eliminate glitches for combinational logic design

Quote:

> Can anybody here give me some general ideas how to eliminate glitches
> for combinational logic design?  Or where can I find this kind of
> knowledge?

Register your outputs?

-andy



Sun, 01 Feb 2004 01:27:00 GMT  
 How to eliminate glitches for combinational logic design
Quote:

> Can anybody here give me some general ideas how to eliminate glitches
> for combinational logic design?  Or where can I find this kind of
> knowledge?

> Thanks a lot,
> mingwei

Just, the principle:
If you draw a KV diagram
(http://tech-www.informatik.uni-hamburg.de/applets/kvd/) try to cover
_all_ 1 to 1 transitions with a loop.

Thats like introducing redundance in your logic:
f(a, b, c) = a & b | c & !b
blow this up to
f(a, b, c) = a & b | c & !b | a & c

Hope this helps

Patrick

--

University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://ra.ti.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713



Sun, 01 Feb 2004 16:26:07 GMT  
 How to eliminate glitches for combinational logic design

Quote:

> > Can anybody here give me some general ideas how to eliminate glitches
> > for combinational logic design?  Or where can I find this kind of
> > knowledge?

> > Thanks a lot,
> > mingwei
> Just, the principle:
> If you draw a KV diagram
> (http://tech-www.informatik.uni-hamburg.de/applets/kvd/) try to cover
> _all_ 1 to 1 transitions with a loop.

> Thats like introducing redundance in your logic:
> f(a, b, c) = a & b | c & !b
> blow this up to
> f(a, b, c) = a & b | c & !b | a & c

> Hope this helps

> Patrick

hi ,
register u r output to avoid glitch problem due to combi logic!

bhooshan



Mon, 02 Feb 2004 19:19:10 GMT  
 How to eliminate glitches for combinational logic design

Quote:



> > > Can anybody here give me some general ideas how to eliminate glitches
> > > for combinational logic design?  Or where can I find this kind of
> > > knowledge?

> > > Thanks a lot,
> > > mingwei
> > Just, the principle:
> > If you draw a KV diagram
> > (http://tech-www.informatik.uni-hamburg.de/applets/kvd/) try to cover
> > _all_ 1 to 1 transitions with a loop.

> > Thats like introducing redundance in your logic:
> > f(a, b, c) = a & b | c & !b
> > blow this up to
> > f(a, b, c) = a & b | c & !b | a & c

> > Hope this helps

> > Patrick

> hi ,
> register u r output to avoid glitch problem due to combi logic!

> bhooshan

Don't know why, but Mingwei wants to avoid glitches in combinational
logic. I just answered this question.

Sure, registered outputs does this too, but then your logic isn't pure
combinational anymore.
Maybe Mingwei thinks about async state machines?

Patrick

--

University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://ra.ti.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713



Mon, 02 Feb 2004 23:50:13 GMT  
 How to eliminate glitches for combinational logic design

Quote:


> > Can anybody here give me some general ideas how to eliminate glitches
> > for combinational logic design?  Or where can I find this kind of
> > knowledge?

> > Thanks a lot,
> > mingwei
> Just, the principle:
> If you draw a KV diagram
> (http://tech-www.informatik.uni-hamburg.de/applets/kvd/) try to cover
> _all_ 1 to 1 transitions with a loop.

> Thats like introducing redundance in your logic:
> f(a, b, c) = a & b | c & !b
> blow this up to
> f(a, b, c) = a & b | c & !b | a & c

> Hope this helps

> Patrick

> --

> University of Mannheim - Dep. of Computer Architecture
> 68161 Mannheim - GERMANY / http://ra.ti.uni-mannheim.de
> Phone: +49-621-181-2720     Fax: +49-621-181-2713

And then you have to persuade the synthesiser not to throw the redundancy
away.


Tue, 03 Feb 2004 07:53:11 GMT  
 How to eliminate glitches for combinational logic design
Quote:



> > > Can anybody here give me some general ideas how to eliminate glitches
> > > for combinational logic design?  Or where can I find this kind of
> > > knowledge?

> > > Thanks a lot,
> > > mingwei
> > Just, the principle:
> > If you draw a KV diagram
> > (http://tech-www.informatik.uni-hamburg.de/applets/kvd/) try to cover
> > _all_ 1 to 1 transitions with a loop.

> > Thats like introducing redundance in your logic:
> > f(a, b, c) = a & b | c & !b
> > blow this up to
> > f(a, b, c) = a & b | c & !b | a & c

> > Hope this helps

> > Patrick

> > --

> > University of Mannheim - Dep. of Computer Architecture
> > 68161 Mannheim - GERMANY / http://ra.ti.uni-mannheim.de
> > Phone: +49-621-181-2720     Fax: +49-621-181-2713

> And then you have to persuade the synthesiser not to throw the redundancy
> away.

You are right, that wouldn't fit in the flow. I also would not use async
FSMs, too.

Patrick
--

University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://ra.ti.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713



Tue, 03 Feb 2004 17:00:18 GMT  
 
 [ 7 post ] 

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