How to eliminate glitches for combinational logic design

Quote:

> > > Can anybody here give me some general ideas how to eliminate glitches

> > > for combinational logic design? Or where can I find this kind of

> > > knowledge?

> > > Thanks a lot,

> > > mingwei

> > Just, the principle:

> > If you draw a KV diagram

> > (http://tech-www.informatik.uni-hamburg.de/applets/kvd/) try to cover

> > _all_ 1 to 1 transitions with a loop.

> > Thats like introducing redundance in your logic:

> > f(a, b, c) = a & b | c & !b

> > blow this up to

> > f(a, b, c) = a & b | c & !b | a & c

> > Hope this helps

> > Patrick

> hi ,

> register u r output to avoid glitch problem due to combi logic!

> bhooshan

Don't know why, but Mingwei wants to avoid glitches in combinational

logic. I just answered this question.

Sure, registered outputs does this too, but then your logic isn't pure

combinational anymore.

Maybe Mingwei thinks about async state machines?

Patrick

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