1364-95 Verilog vs Verilog-XL 
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 1364-95 Verilog vs Verilog-XL

hi,
In 1364-95, page 14 syntax 3-1, it says that delay_value can be an
unsigned number, a parameter, or a constant mintypmax number. I
interpreted this initially to mean that the delay_value can only be a
constant. But in XL, the same definition includes and identifier. My
simulator accepts a time type variable for a delay value (#time_var
foo = ~ foo;) and it behaves as one would expect (the frequency
changes when time_var changes). Does 1364-95 really mean a constant
delay ? If yes, why did they change it from XL definition? and are
there any simulators which force this? What does 1364-01 say about
this?
Muzaffer

FPGA DSP Consulting
http://www.*-*-*.com/



Wed, 24 Sep 2003 15:15:00 GMT  
 
 [ 1 post ] 

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