Verilog resistor models 
Author Message
 Verilog resistor models

Recenct threads surrond the classic resistor model.  I have two
suggestions, neither of which is entirely bullet proof.

First, at the schematic level you can use a verilog_name property
to select between one of two modules to instantiate for the resistor.

If a pullup is wanted, a module resp is specified:

Quote:
>module resp(a,b);

>    inout a,b;
>    rtran   I0(a,b);

>endmodule

If a series resistor is desired the module ress is selected:

Quote:
>module ress(a,a);

>input a;

>endmodule

(I wish I could take credit for the ress, but it is a technique
Cadence uses to netlist I/O pins from schematic in Composer - and
yes it does work like a bi-directional assign statement).

Unfortunately, for this system, the user must selectively change
module names for at least half of his resistors (ie. you can
default the property to either resp or ress) on his/her schematic.

A second technique is to use verilog paramter/defparam to select
both series/pullup and direction (I can't think of a way to do
a bi-directional condtional assignment).  This looks like:

Quote:
>module res (A, B);
>inout A,B;
>reg cntl,cntl1,cntl2;
>parameter s = 0,                // default to weak rtran
>                                // set param to 1 if strong buf req'd

>          atob = 1;             // default direction of strong buf
>                                // is a -> b (atob = 1).  For b -> a,
>                                // change atob = 0.  Unused if s = 0!

>rtranif1 I0(B,A,cntl);
>bufif1  I1(B,A,cntl1);
>bufif1  I2(A,B,cntl2);

>initial
>        begin
>        if ((s == 1)&&(atob == 1))
>                begin
>                cntl1 = 1;
>                cntl2 = 0;
>                cntl = 0;
>                end
>        if((s == 1)&&(atob == 0))
>                begin
>                cntl1 = 0;
>                cntl2 = 1;
>                cntl = 0;
>                end
>        if (s == 0)
>                begin
>                cntl1 = 0;
>                cntl2 = 0;
>                cntl = 1;
>                end
>        end
>endmodule

Again, the user must override a bunch of default parameters to get the
model to work for different applications.  

I would be very interested in hearing about alternate implementations.

Larry Atkinson
Sr. Simulation and Modelling Engineer
Mitel Corporation



Tue, 07 Jan 1997 21:28:17 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. Creating a resistor model for system level synthesis

2. Updated Pullup resistor model with delay

3. Modeling a pullup resistor in VHDL simulation

4. HELP in model a pull-up resistor....

5. help with VHDL resistor model

6. c model convert to verilog/VHDl model

7. How to model the transmission gate in Verilog without using tran (Behaviour model)

8. PLI model vs. Verilog model

9. Verilog ***** Verilog ***** Verilog ***** Verilog

10. Object models, Domain models, Application models, and MVC?

11. Object models, Domain models, Application models, and MVC?

12. The Verilog PLL model?

 

 
Powered by phpBB® Forum Software