The inertial delay model 
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 The inertial delay model

Quote:

>Is the inertial delay model generally considered to be
>a major disadvantage of Verilog ?
>Why do people tolerate it ?

Not really. The reason being very simple:
        a) Either you do not care that much about delay accuracy, and
           then Intertial delay is fine,

        b) Or if you care, then you probably want to use Path delay
           (aka pin-to-pin delays). With Path delays in Verilog, you can
           specify either Transport delay, Inertial Delay, or even a mode
           in between where the pulse is propagated as an unknown. This
           selection can be done on a path per path basis, although most
           ASIC houses use the same mode for all path within the simulation.

           Usually, they choose:
                If pulse > Pathdelay -> Propagate the pulse
                If pulse < Pathdelay -> Propagate the pulse as an 'X'

In fact, Verilog offers more than most simulators in the area of
accurate delay modeling.

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Project Manager SMCS            UUCP:   ...!uunet!cadence!patrick
Eucad Ltd                       Phone:  (33-1) 6928 5485
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_________________________________________________________________

Project Manager SMCS            UUCP:   ...!uunet!cadence!patrick
Eucad Ltd                       Phone:  (33-1) 6928 5485



Tue, 14 Jun 1994 17:32:16 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. This week's Coding tip: modeling combinational logic with inertial delays

2. This week's Coding tip: modeling combinational logic with inertial delays

3. Avoiding inertial delay in delay lines

4. Transport Delay and Inertial Delay

5. Transport Delay Vs Inertial Delay

6. Inertial and transport delay in Verilog

7. Inertial Delay in Aldec 4.2?

8. Inertial and transport delay in Verilog

9. Transport vs. Inertial....ooops (DELAY item)

10. Transport/Inertial DElay's

11. inertial vs. transport delay

12. Adding delay to a `protected (encrypted) model

 

 
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