Data Input from File?? 
Author Message
 Data Input from File??

I am looking for a method that will allow me to read test vectors from a
file into my simulation test bench.  In VHDL, I use the READLINE statement
from the TEXTIO package.  I have seen no such functionality in Verilog,
other that $readmemh, which requires me to construct a RAM and memory
interface to drive test vectors onto an input bus.

Is anyone aware of an extension to Verilog or any other way to simply do
what I need?
A direct email response would be preferred.

Thank you.

Todd Shelton
Sorenson Vision Inc.



Fri, 01 Jun 2001 03:00:00 GMT  
 Data Input from File??
Use "readmemh" or "readmemb"
Quote:

> I am looking for a method that will allow me to read test vectors from a
> file into my simulation test bench.  In VHDL, I use the READLINE statement
> from the TEXTIO package.  I have seen no such functionality in Verilog,
> other that $readmemh, which requires me to construct a RAM and memory
> interface to drive test vectors onto an input bus.

> Is anyone aware of an extension to Verilog or any other way to simply do
> what I need?
> A direct email response would be preferred.

> Thank you.

> Todd Shelton
> Sorenson Vision Inc.




Sat, 02 Jun 2001 03:00:00 GMT  
 Data Input from File??
Sorry,

I did not read the entire question....
Nevermind....

Quote:

> Use "readmemh" or "readmemb"


> > I am looking for a method that will allow me to read test vectors from a
> > file into my simulation test bench.  In VHDL, I use the READLINE statement
> > from the TEXTIO package.  I have seen no such functionality in Verilog,
> > other that $readmemh, which requires me to construct a RAM and memory
> > interface to drive test vectors onto an input bus.

> > Is anyone aware of an extension to Verilog or any other way to simply do
> > what I need?
> > A direct email response would be preferred.

> > Thank you.

> > Todd Shelton
> > Sorenson Vision Inc.




Sat, 02 Jun 2001 03:00:00 GMT  
 Data Input from File??
I've been happy with a freeware PLI package I got from
the web called "read.c".  It allows formatted input into
verilog in a fairly straightforward manner.  I've used
it with Verilog-XL as well as VCS.  There are a couple
of bugs, but they're pretty easy to fix.  I got it from
"Celia's Verilog & EDA Web Page" at
www.europa.com/~celiac/ver_eda.  Follow the "PLI information"
link, then the "examples" section.

        Paul Dormitzer
        Broadband Access Systems



Sat, 02 Jun 2001 03:00:00 GMT  
 Data Input from File??
Thanks,

I found read.c on my own earlier this morning and got it going (it was a
little tricky to get it linked in under my ModelTech simulator).  It appears
to work great and do just what I wanted.  Do you recall what the bugs you
experienced were?  What should I be on the look out for?

Thanks again.

Todd Shelton
Sorenson Vision Inc.

Quote:

>I've been happy with a freeware PLI package I got from
>the web called "read.c".  It allows formatted input into
>verilog in a fairly straightforward manner.  I've used
>it with Verilog-XL as well as VCS.  There are a couple
>of bugs, but they're pretty easy to fix.  I got it from
>"Celia's Verilog & EDA Web Page" at
>www.europa.com/~celiac/ver_eda.  Follow the "PLI information"
>link, then the "examples" section.

> Paul Dormitzer
> Broadband Access Systems



Sat, 02 Jun 2001 03:00:00 GMT  
 Data Input from File??

Quote:

> I've been happy with a freeware PLI package I got from
> the web called "read.c".  It allows formatted input into
> verilog in a fairly straightforward manner.  I've used
> it with Verilog-XL as well as VCS.  There are a couple
> of bugs, but they're pretty easy to fix.  I got it from
> "Celia's Verilog & EDA Web Page" at
> www.europa.com/~celiac/ver_eda.  Follow the "PLI information"
> link, then the "examples" section.

>    Paul Dormitzer
>    Broadband Access Systems

        Note also that a complete set of system tasks for file input
have been approved for the Draft Verilog-1998 standard, so presumably
some time next year if all goes well, you will have this capability
built in to your commercial verilog simulator.

--

   /\//    SureFire Verification Inc.   408-374-4100 x 100
  /\///\   <http://www.surefirev.com>   408-374-4174 FAX
 _\///\/        Formerly Silicon Sorcery
  \//\/    Get my verilog emacs mode from
    \/     <http://www.surefirev.com/verilog-mode.html>



Sun, 03 Jun 2001 03:00:00 GMT  
 Data Input from File??
One bug I recall having found and fixed related to the code assuming
that malloced memory was intialized to NULLs. This maybe true on SunOS
but wasn't on HPUX. In one of the string operations, the ending
characters was not a NULL on HPUX for this reason and was resulting in
crash.


think still maintains the code, if bugs are reported to him. I had used
rev 1.5 last.

You may contact him for latest version.

-Ashutosh

Quote:

> Thanks,

> I found read.c on my own earlier this morning and got it going (it was a
> little tricky to get it linked in under my ModelTech simulator).  It appears
> to work great and do just what I wanted.  Do you recall what the bugs you
> experienced were?  What should I be on the look out for?

> Thanks again.

> Todd Shelton
> Sorenson Vision Inc.


> >I've been happy with a freeware PLI package I got from
> >the web called "read.c".  It allows formatted input into
> >verilog in a fairly straightforward manner.  I've used
> >it with Verilog-XL as well as VCS.  There are a couple
> >of bugs, but they're pretty easy to fix.  I got it from
> >"Celia's Verilog & EDA Web Page" at
> >www.europa.com/~celiac/ver_eda.  Follow the "PLI information"
> >link, then the "examples" section.

> > Paul Dormitzer
> > Broadband Access Systems

--
Ashutosh Varma                                           Axis Systems
Senior Application Specialist                          209 Java Drive

Phone: (408)588-2000 x143                          Fax: (408)588-1662


Mon, 04 Jun 2001 03:00:00 GMT  
 
 [ 7 post ] 

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