bug in Wellspring Veriwell? 
Author Message
 bug in Wellspring Veriwell?

I've been trying to run some simulations with the free version of
Wellspring's Veriwell (version 2.0.0).  Trying to compile this example
from the Verilog quick reference card for an edge-triggered D
flipflop:

primitive dff(QN, D, CP, R, S);
output QN;
input D, CP, R, S;
reg QN;
table
1 (01) 0 0 : ? : 0;
1 (01) 0 x : ? : 0;
? ? 0 x : 0 : 0;
0 (01) 0 0 : ? : 1;
0 (01) x 0 : ? : 1;
? ? x 0 : 1 : 1;
1 (x1) 0 0 : 0 : 0;
0 (x1) 0 0 : 1 : 1;
1 (0x) 0 0 : 0 : 0;
0 (0x) 0 0 : 1 : 1;
? ? 1 ? : ? : 1;
? ? 0 1 : ? : 0;
? n 0 0 : ? : -;
* ? ? ? : ? : -;
? ? (?0) ? : ? : -;
? ? ? (?0) : ? : -;
? ? ? ? : ? : x;
endtable
endprimitive

I get a message for line 22 ("? ? ? ? : ? : x;") of "error: level vs
level table entry conflict".  Is this a glitch in Veriwell, or is the
reference card in error?

        Mike Caplinger, MSSS



Sun, 14 Dec 1997 03:00:00 GMT  
 
 [ 1 post ] 

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