Multiple instances of mem, diff data files? 
Author Message
 Multiple instances of mem, diff data files?

Here's an interesting problem I've run into.

After designing a memory component and then attempting to use it
in a system I'm developing, I've run into a bug--my design uses
multiple instances of this ROM, but I haven't been able to find
a method to get verilog to allow me to input a different data
file for each instance of the device. Is there a way to do this,
or must I create several different copies of the module, and  
manipulate files in that manner?  Thanks!

John Roe



Sun, 13 Apr 1997 05:55:49 GMT  
 Multiple instances of mem, diff data files?
|> Here's an interesting problem I've run into.
|>
|> After designing a memory component and then attempting to use it
|> in a system I'm developing, I've run into a bug--my design uses
|> multiple instances of this ROM, but I haven't been able to find
|> a method to get verilog to allow me to input a different data
|> file for each instance of the device. Is there a way to do this,
|> or must I create several different copies of the module, and  
|> manipulate files in that manner?  Thanks!
|>
|> John Roe

You could use defparam:

--- cut here ---
module ROM;

parameter ImageFile = "ROM.image";

// some Verilog or PLI stuff to read the ImageFile

initial
   $display("%m uses ROM image file: %s",ImageFile);

endmodule

module test;

defparam rom1.ImageFile = "ROM-1.image",
         rom2.ImageFile = "ROM-2.image",
         rom3.ImageFile = "ROM-3.image";

ROM rom1(),
    rom2(),
    rom3();

endmodule
--- cut here ---

Running this gives:

Compiling source file "paramfile.v"
Highest level modules:
test

test.rom1 uses ROM image file: ROM-1.image
test.rom2 uses ROM image file: ROM-2.image
test.rom3 uses ROM image file: ROM-3.image
6 simulation events
CPU time: 0.2 secs to compile + 0.2 secs to link + 0.0 secs in simulation
End of VERILOG-XL 1.8   Oct 27, 1994  11:04:54

Hope this is what you wanted.
Regards,
Petter

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Mon, 14 Apr 1997 18:12:04 GMT  
 Multiple instances of mem, diff data files?
: Here's an interesting problem I've run into.

: After designing a memory component and then attempting to use it
: in a system I'm developing, I've run into a bug--my design uses
: multiple instances of this ROM, but I haven't been able to find
: a method to get verilog to allow me to input a different data
: file for each instance of the device. Is there a way to do this,
: or must I create several different copies of the module, and  
: manipulate files in that manner?  Thanks!

: John Roe

:  

We used parameters to define the default in the ROM file and then use
defparam to modify it for each instance.

An example

module ROM(...);
...
parameter LOADFILE = "rom.da";  //name of datafile file
...
initial
        $readmemh(LOADFILE, buff) ;
...
endmodule

module manyROM;
...
ROM i1(...);
ROM i2(...);
defparam i1.LOADFILE = "rom1.dat" ;
defparam i2.LOADFILE = "rom2.dat" ;
...
endmodule

This works for us in the work we have done.

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Mon, 14 Apr 1997 23:19:15 GMT  
 
 [ 3 post ] 

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