Combining signals (P1364 vs. Verilog-XL) 
Author Message
 Combining signals (P1364 vs. Verilog-XL)

Can somebody explain why the method for resolving multiple drivers of
wires as described in P1364 is wrong, or correct my misunderstanding?

The code below should have the behaviour of figures 7-17, 7-18 and 7-19
when producing my_36X, but they don't. According to those figures, We0
combined with StH should produce 36X, but Verilog-XL produces StX.

Figure 7-21 is also in there somewhere, but as I can't produce a 26X, I
use a 36X from an AND gate (see real_36X) and combine this with Pu1
(explicitly as my_Pu1, but the result is the same if I use pullup).
Verilog-XL once again yields StX, instead of the P1364's claimed 561
(651?) signal.

I'd really like to understand signal resolution if anyone can help.
Thanks

------------------------------

module EXP_084c();

   reg one, zero, unk;
   initial
      begin
         one = 1;
         zero = 0;
         unk = 1'bx;
      end // initial begin

   pullup (my_Pu1);
   initial #20000 $display("my_Pu1 = %v", my_Pu1);

   // The production of my_36X is lifted from P1364 fig 7-16

   and (strong1, highz0) A1(my_StH, one, unk);
   initial #20000 $display("my_StH = %v", my_StH);

   and (strong1, weak0)  A2(my_We0, zero, zero);
   initial #20000 $display("my_We0 = %v", my_We0);

   rtran (my_We0, my_Me0);
   initial #20000 $display("my_Me0 = %v", my_Me0);

   wire my_36X;
   assign my_36X = my_StH;
   assign my_36X = my_We0;

   wire pullup_my_36X;
   assign pullup_my_36X = my_36X;
   assign pullup_my_36X = my_Pu1;
   initial #20000 $display("\nmy_36X(%v) with pullup = %v",
                           my_36X, pullup_my_36X);

   wire my_26X;
   assign my_26X = my_StH;
   assign my_26X = my_Me0;

   wire pullup_my_26X;
   assign pullup_my_26X = my_26X;
   assign pullup_my_26X = my_Pu1;
   initial #20000 $display("\nmy_26X(%v) with pullup = %v",
                           my_26X, pullup_my_26X);

   and (weak0, strong1) A3(real_36X, unk, unk);

   wire pullup_real_36X;
   assign pullup_real_36X = real_36X;
   assign pullup_real_36X = my_Pu1;
   initial #20000 $display("\nreal_36X(%v) with pullup = %v",
                           real_36X, pullup_real_36X);

   initial #20000 $display;

endmodule // EXP_084c

/* with or without +switchxl

my_Pu1 = Pu1
my_StH = StH
my_We0 = St0
my_Me0 = St0

my_36X(StX) with pullup = StX

my_26X(StX) with pullup = StX

real_36X(36X) with pullup = StX

*/
--
Daryl Stewart
RA to EPSRC Verilog Formal Equivalence Project
http://www.*-*-*.com/ :80/users/djs1002/verilog.project/



Mon, 05 Jul 1999 03:00:00 GMT  
 Combining signals (P1364 vs. Verilog-XL)

Quote:

> Can somebody explain why the method for resolving multiple drivers of
> wires as described in P1364 is wrong, or correct my misunderstanding?

> The code below should have the behaviour of figures 7-17, 7-18 and 7-19
> when producing my_36X, but they don't. According to those figures, We0
> combined with StH should produce 36X, but Verilog-XL produces StX.

> Figure 7-21 is also in there somewhere, but as I can't produce a 26X, I
> use a 36X from an AND gate (see real_36X) and combine this with Pu1
> (explicitly as my_Pu1, but the result is the same if I use pullup).
> Verilog-XL once again yields StX, instead of the P1364's claimed 561
> (651?) signal.

> I'd really like to understand signal resolution if anyone can help.
> Thanks

Howdy,

If I wire up the output of the AND gates as in fig 7-16:
   and (strong1, highz0) A1(temp, one, unk);

   and (strong1, weak0)  A2(temp, zero, zero);

I get
temp = 36X

You are then connecting a Pu1 to your 36X and rule defined in 7.11.3
applies, hence the 3 gets elimated resulting in 6X which now gets
displayed as a mnemonic StX (as defined in table 14-5) and described in
14.1.1.5.

Hope this helps,
Regards, Jurgen.



Tue, 06 Jul 1999 03:00:00 GMT  
 Combining signals (P1364 vs. Verilog-XL)

Quote:


> > Can somebody explain why the method for resolving multiple drivers of
> > wires as described in P1364 is wrong, or correct my misunderstanding?

<snip>

Quote:
> > Thanks

> Howdy,

> If I wire up the output of the AND gates as in fig 7-16:
>    and (strong1, highz0) A1(temp, one, unk);

>    and (strong1, weak0)  A2(temp, zero, zero);

> I get
> temp = 36X

> You are then connecting a Pu1 to your 36X and rule defined in 7.11.3
> applies, hence the 3 gets elimated resulting in 6X which now gets
> displayed as a mnemonic StX (as defined in table 14-5) and described in
> 14.1.1.5.

> Hope this helps,
> Regards, Jurgen.

Thanks - I hadn't thought of using implied nets, but I'm more confused
now.

I agree temp holds (what I believe to be) the correct value, but do you
know why using an explicitly declared net does not work. Surely I should
get my_36X = 36X in the following?

   and (strong1, highz0) A1(my_StH, one, unk);
   and (strong1, weak0)  A2(my_We0, zero, zero);

   wire my_36X;
   assign my_36X = my_StH;
   assign my_36X = my_We0;

Also, 36X with a pullup connected CAN give 651 if I use implied nets:

----------------------------------------
module EXP_086();

   reg one, zero, unk;
   initial
      begin
         one = 1;
         zero = 0;
         unk = 1'bx;
      end // initial begin

   and (strong1, highz0) A1(temp, one, unk);
   and (strong1, weak0)  A2(temp, zero, zero);

   pullup (temp);

   initial #10 $display ("temp = %v", temp);

endmodule // EXP_086

/*
Compiling source file "experiment.086.cv"
Highest level modules:
EXP_086

temp = 651
10 simulation events + 8 accelerated events
CPU time: 0.2 secs to compile + 0.1 secs to link + 0.0 secs in
simulation
End of VERILOG-XL 2.2.1   Jan 20, 1997  16:31:08
*/
----------------------------------------

This behaviour agrees with fig 7-21, although 7.11.1 actually makes no
mention of including the unambiguous signal in the result.

What's going on???
--
Daryl Stewart
RA to EPSRC Verilog Formal Equivalence Project
http://www.cl.cam.ac.uk:80/users/djs1002/verilog.project/



Fri, 09 Jul 1999 03:00:00 GMT  
 
 [ 3 post ] 

 Relevant Pages 

1. 1364-95 Verilog vs Verilog-XL

2. VERILOG-XL CWAVES Search for a Signal

3. Verilog-XL/NC-Verilog Event Order

4. Retrieving protected Verilog code in Verilog-XL??

5. Verilog 2.7 (Verilog-XL) Warning message

6. IEEE draft standard P1364 verilog: sized constants

7. IEEE draft standard P1364 verilog: sized constants

8. P1364: parameters: integer vs. real

9. remove a sinewave component from a combined signal

10. combining signals into array

11. Combining signals as input to a port

12. combine tv and computer signals?

 

 
Powered by phpBB® Forum Software