library/design instance resolution 
Author Message
 library/design instance resolution

(I don't have a simulator around to test this.)

In a design you have (psuedo-code):

module A
endmodule

module B
instance C
endmodule

In your library you have:

module A
endmodule

module C
instance A
endmodule

Which module A will be used for the instance in library cell C?
Will it use the design module A that it has already processed?
Or will it use the cell in the library?

Todd.



Sat, 31 Dec 2005 04:34:58 GMT  
 library/design instance resolution
Design module A.

Shalom

Quote:

> (I don't have a simulator around to test this.)

> In a design you have (psuedo-code):

> module A
> endmodule

> module B
> instance C
> endmodule

> In your library you have:

> module A
> endmodule

> module C
> instance A
> endmodule

> Which module A will be used for the instance in library cell C?
> Will it use the design module A that it has already processed?
> Or will it use the cell in the library?

> Todd.

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Sat, 31 Dec 2005 22:12:23 GMT  
 library/design instance resolution
Hi Todd,

Quote:

> (I don't have a simulator around to test this.)

> In a design you have (psuedo-code):

> module A
> endmodule

> module B
> instance C
> endmodule

> In your library you have:

> module A
> endmodule

> module C
> instance A
> endmodule

  I think it is tool dependent, let me explain why I think so before I
get any flame :-)

1. If you use a compiled code simulator such as NCSIM and ASSUMING
that you compile design.module.A first and then library.module.A (in
to the same work library) and finally module C, NCSIM will pick up
library.module.A as that has been compiled the last and would have
over-written the previous image.

2. Things would be different if you different libraries to compile
into, of-course. Then I think NCSIM has some way of forcing which one
to pick (similar to CHDL/Verilog-2001 configuration, but less
powerful).

3. I haven't tried such a case in Modelsim, neither in VCS nor in VXL,
but I know that if you have 2 modules with same name, VCS & VXL would
exit with error.

Regards,
Ajeetha
http://www.noveldv.com


and say you don't have access to a simulator, no flame intended, just
curious as I know more and more individuals prefer using the FREE
version of Modelsim that comes with Webpack, I am a happy user of that
too :-)

- Show quoted text -

Quote:
> Which module A will be used for the instance in library cell C?
> Will it use the design module A that it has already processed?
> Or will it use the cell in the library?

> Todd.



Sun, 01 Jan 2006 01:07:41 GMT  
 library/design instance resolution

Quote:

> Regards,
> Ajeetha
> http://www.noveldv.com


> and say you don't have access to a simulator, no flame intended, just
> curious as I know more and more individuals prefer using the FREE
> version of Modelsim that comes with Webpack, I am a happy user of that
> too :-)

Well, I can get access to the model tech one, but then I have to deal
with the pita of getting the licensing, etc, set up.  I should have mentioned
that what I really want is how XL does it, and there isn't any way I'll be
able to get ahold of it.  Todd.


Sun, 01 Jan 2006 03:49:48 GMT  
 library/design instance resolution
Could you elaborate why?  Is this with XL?

Using design module A seems like the wrong thing that
should be done here.  (The library designer wouldn't be
able to control functionality, a simple name conflict will
cause a different module to be bound, it could introduce
unwanted order dependencies, and the ports of these
modules could even be different, which may or may not
report an error.)

OTOH, if the tool is using a simple single symbol table,
then this situation would happen.  It would also give the
dubious benefit of allowing replacement of library cells
without physically modifying the library.

Quote:

> Design module A.

> Shalom


> > (I don't have a simulator around to test this.)

> > In a design you have (psuedo-code):

> > module A
> > endmodule

> > module B
> > instance C
> > endmodule

> > In your library you have:

> > module A
> > endmodule

> > module C
> > instance A
> > endmodule

> > Which module A will be used for the instance in library cell C?
> > Will it use the design module A that it has already processed?
> > Or will it use the cell in the library?



Sun, 01 Jan 2006 03:58:50 GMT  
 library/design instance resolution

Quote:

> Could you elaborate why?  Is this with XL?

I presume we are talking about library files referenced with
-y or -v on the command line.

The reason it works this way is that this is how it is defined
to work.  The library files are only searched for modules that
were not defined in the design.

This wasn't designed as a complex library and binding mechanism.
It was just a way of accessing a source file containing a library
of cells without having all the unused ones unintentionally turn
into top-level modules.  Note that XL doesn't even fully compile
the library files.  It just textually scans them until it finds
something that looks like a declaration for the unresolved module
and then compiles that one module.  It doesn't even know that the
other module definition was there (or even that the text ahead of
the module definition was legal Verilog).  Since XL does not do
separate pre-compilation, it does a lot of things differently
from more conventional compilers.

The `uselib directive provides somewhat more sophisticated
library mechanisms.



Mon, 02 Jan 2006 08:01:29 GMT  
 
 [ 6 post ] 

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