Job Duties and Responsibilities:

Deep submicron ASIC design with emphasis on physical layout.  Perform
physical design using the latest Cadence tools and methodologies, including
floorplanning, timing closure and verification.   Become part of a design
team for the development of high integration and high performance products.
Interface to customers and recommend design flows.

Experience:

BSEE or MSEE
Prior experience with auto place and route tools, design methodologies and
concepts.  Minimum of two years experience with Avant! (Planet) or Cadence
(Silicon Ensemble) tools is required.  Experience with RTL design, synthesis
and static timing analysis is preferred.

Contact:
  SIS Microelectronics