Beginner Verilog Question 
Author Message
 Beginner Verilog Question

Quote:

>The following is a Verilog module I found at
> http://www.*-*-*.com/

>Can someone please explain the meaning of the question-marked line below. I
>don't understand what condition the if expression is attempting to test.
>Doesn't AND have higher priority than equality? And isn't X AND X always equal
>to X? Like I said, I am a beginner.

This code looks like it was written by someone who is more familiar with
VHDL than verilog. I assume that the funtionality that they are
trying to get is the VHDL if clock event and clock equals one.

Quote:
>module ff_clk (d, en, clk, clr, q);
>input d, en, clk, clr;
>output q;
>reg q;

Should be written:


begin
  if (clr == 1'b0)
  begin
    q <= 1'b0;
  end
  else if (en == 1'b1)
  begin
    q <= d;
  end
end

You could write it other ways as well, but the above will synthesize to
a d flip-flop with a negitive clear and a syncronous, positive enable.
You are correct that the & takes precidence over the ==, but in this
case it didn't matter since they are simply checking if a one bit
vector equal one. if (clk) and if (clk == 1'b1) evaluate to the same
value and (clk & clk) evaluates to the same value as clk.

Quote:

>        begin
>                if (clr == 1'b 0)
>                        begin
>                                q <= 1'b 0;
>                        end
>                else if (clk & clk == 1'b 1 )  // ???
>                        begin
>                                if (en == 1'b 1)
>                                        begin
>                                                q <= d;
>                                        end
>                        end
>        end
>endmodule

Hope this helps some....
--
-----------------------------------------------------------------------------
--Celia Clause                    Celia's Verilog/EDA web page:



Sat, 20 May 2000 03:00:00 GMT  
 Beginner Verilog Question

I will explain this to you. Some very confused and twisted person who
knows little about RTL and hence is at Actel has screwed up and left a
mess for you to untangle. Ignore this and find better examples of
code.

Quote:

>The following is a Verilog module I found at
>http://wwwtest.actel.com/HLD/veri/veri5.html

>Can someone please explain the meaning of the question-marked line below. I
>don't understand what condition the if expression is attempting to test.
>Doesn't AND have higher priority than equality? And isn't X AND X always equal
>to X? Like I said, I am a beginner.

>module ff_clk (d, en, clk, clr, q);
>input d, en, clk, clr;
>output q;
>reg q;

>        begin
>                if (clr == 1'b 0)
>                        begin
>                                q <= 1'b 0;
>                        end
>                else if (clk & clk == 1'b 1 )  // ???
>                        begin
>                                if (en == 1'b 1)
>                                        begin
>                                                q <= d;
>                                        end
>                        end
>        end
>endmodule

>-----
>[nb: my email address is modified to foil auto-mailers]



Wed, 24 May 2000 03:00:00 GMT  
 
 [ 2 post ] 

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