Reading inputs from a file 
Author Message
 Reading inputs from a file

Hi:

Could anyone out there tell me how to give the inputs to a circuit
described in Verilog from a file.

The problem I have is this.  My circuits have more than one inputs.  So,
my inputs are vectors.  A new input vector has to be applied after each
clock pulse.  The input file I have is a series of 1's and 0's.  So, I
need to get chunks of inputs (whose length is equal to the length of the input
vector) from the input file and assign it to the input vector.

At the moment, I assign the whole input sequence to an array,and read
chunks of it in a "for" loop.  The problem with this is, I have to change
the verilog file whenever I need to apply a different sequence (when the
new sequence has a different length - I need to adjust my loops too !!!).

So, I'd really appreciate if someone could tell me how to read the inputs
from a file.

--Niranjan

------------------------------------------------------------------------------


409 Dana Reserch Center
Northeastern University                
Boston, MA 02115                                
------------------------------------------------------------------------------



Mon, 13 Jan 1997 04:57:17 GMT  
 Reading inputs from a file
In general, the only way to read inputs from a file using verilog is to
load them into an array. There are a couple of things you can do:

1) Write a PLI task that does what you want.

2) Imbed a control field in the pattern stream.

What I generally do is to create a state machine associated with the input
stream. I use yacc or perl to write a stimulus compiler. I use a sparse
memory model ( one that is dynamically allocated and written using the PLI,
there is one that comes with Verilog-XL, although it generally pays off
to write your own, simply so you know where to add the features you want ).

The state machine is a controller for the stimulus generator. It reads the bits
in a reserved field in the pattern stream. It may be as simple as a mechanism
to tell you when the stream has ended.

This approach works pretty well. If there is some compiling that has to be
done to the stimulus source file, it is better to do it before hand, rather
than trying to do it in Verilog: 1) It's easier to debug. 2) consumes less
simulation time.

If your stimulus file is so big that this has a significant effect on memory
requirements, I would recommend some form of compression.

                                        John Williams



Tue, 14 Jan 1997 15:42:47 GMT  
 Reading inputs from a file
I'm not sure if you are already doing this but you could get
the readmemh() function in verilog to read the inputs from
a file.

Marlan Winter

: Hi:

: Could anyone out there tell me how to give the inputs to a circuit
: described in Verilog from a file.

: The problem I have is this.  My circuits have more than one inputs.  So,
: my inputs are vectors.  A new input vector has to be applied after each
: clock pulse.  The input file I have is a series of 1's and 0's.  So, I
: need to get chunks of inputs (whose length is equal to the length of the input
: vector) from the input file and assign it to the input vector.

: At the moment, I assign the whole input sequence to an array,and read
: chunks of it in a "for" loop.  The problem with this is, I have to change
: the verilog file whenever I need to apply a different sequence (when the
: new sequence has a different length - I need to adjust my loops too !!!).

: So, I'd really appreciate if someone could tell me how to read the inputs
: from a file.
:  

: --Niranjan

: ------------------------------------------------------------------------------


: 409 Dana Reserch Center
: Northeastern University                      
: Boston, MA 02115                              
: ------------------------------------------------------------------------------



Tue, 14 Jan 1997 22:25:58 GMT  
 Reading inputs from a file
In response to various questions on how to use memories in Verilog,
I have placed a file "gatebnch.tar.Z" compressed tar directory available
by anonymous ftp from site "ftp.crl.com" in directory /ftp/users/ro/sjmeyer/.
It contains a 14k gate hierarchical circuit consisting of chains of not
gates that uses $readmem and $getpattern.  The directory contains a memory
data file for running the model and expected output.

The circuit is actually intended as an answer to the CMU benchmarks from the
1993 IVC conference since those bench marks do not contain any gates with
delays.  I think it is much harder to simulate gate level models fast because
Verilog requires inertial delay rescheduling.  Also the benchmark contains
the sort of test pattern application method an ASIC vendor will probably
require before signing off a design.
/Steve
--
Steve Meyer                             Phone: (415) 296-7017
Pragmatic C Software Corp.              Fax:   (415) 781-1116

San Francisco, CA 94104



Sun, 19 Jan 1997 10:57:37 GMT  
 
 [ 4 post ] 

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