Declaring output as reg creates new port 
Author Message
 Declaring output as reg creates new port

Hello,

I'm new to hardware programming and verilog.
I'm using multisim and the built in verilog simulator.

As I understood it in the tutorials I've read, I have to declare an
output as register to assign something. I've created the following code:

module test(in, out);
input in;
output out;
reg out;


   out = ~in;
endmodule

The code compiles fine, but when I want to start the simulation I get an
error message that I have one input and 2 inouts and that doesn't match
the device I've created.

If I use a not-gate instead of the assignment, I don't get this message.

How can I solve this problem?

Thanks,

Hendrik vom Lehn



Sat, 03 Sep 2005 05:33:06 GMT  
 Declaring output as reg creates new port
Hi!
Check your simulator, by changing the port names to something like
ina, outa, maybe this simulator initially supported VHDL and then they
ported it to support verilog.

Rajkumar...


Quote:
> Hello,

> I'm new to hardware programming and verilog.
> I'm using multisim and the built in verilog simulator.

> As I understood it in the tutorials I've read, I have to declare an
> output as register to assign something. I've created the following code:

> module test(in, out);
> input in;
> output out;
> reg out;


>    out = ~in;
> endmodule

> The code compiles fine, but when I want to start the simulation I get an
> error message that I have one input and 2 inouts and that doesn't match
> the device I've created.

> If I use a not-gate instead of the assignment, I don't get this message.

> How can I solve this problem?

> Thanks,

> Hendrik vom Lehn



Sat, 03 Sep 2005 15:05:40 GMT  
 
 [ 2 post ] 

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