** ASIC Designers Wanted For Next Week's Great ESDA Shootout ** 
Author Message
 ** ASIC Designers Wanted For Next Week's Great ESDA Shootout **

   Next week at the HP Design SuperCon '96 I'll be running an ESDA Shootout
on Tuesday afternoon.   (Our goal is to determine whether the ESDA tools
like those sold by i-Logix, Summit, and Speed can do better or worst than
everyday engineers designing ASIC's using plain old "vi" or EMACS.)  Given
90 minutes, ASIC designers will be asked to hand code a small state machine
and then to synthesize it to gates.  The ESDA Vendors will be sweating it out
creating the *same* design using *their own* ESDA tools!

   The top hand-coding ASIC designers who produce the fastest running
gate-level designs will win instant fame (in the write-up of the contest)
with the best winning an HP color laser printer!  Since we don't have an
infinite number of workstations available, if you're interested in being a

so we can get an estimated head count.

   NAME:_________________________   Phone Number:____________________
   e-mail address:___________________________________________________
   Prefered HDL (Verilog or VHDL):___________________________________

  Oh, don't forget to come to the panel discussion the next day (Wednesday,
Jan. 31st) to see the ESDA vendors either gloat on their victories or squirm
trying to explain why their tools couldn't cut it.  Or, if things go awry,
you could find the contest judge (me) sweating it out trying to explain why
things got screwed up!  :^)
                              - John Cooley
                                Part Time EDA Consumer Advocate
                                Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3881 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Tue, 14 Jul 1998 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. *** The Great ESDA Shootout ***

2. (Verilog) Testbenches For The Great ESDA Shootout

3. (VHDL) Testbenches For The Great ESDA Shootout

4. *** The Great ESDA Shootout ***

5. (Verilog) Testbenches For The Great ESDA Shootout

6. (VHDL) Testbenches For The Great ESDA Shootout

7. ASIC DESIGNER wanted for STARTUP-COMPANY

8. Rochester, NY: IC/ ASIC designers wanted

9. San-Jose, CA: ASIC designers wanted

10. San-Jose, CA - ASIC Designers wanted

11. ASIC Designers wanted in UK

12. wanted: Talented ASIC designers.

 

 
Powered by phpBB® Forum Software