ASIC Design Engineer for Silicon Graphics, Mountain View, CA 
Author Message
 ASIC Design Engineer for Silicon Graphics, Mountain View, CA

Silicon Graphics has a new open position in its Mountain View headquarters for
an ASIC design engineer. This member of the technical staff (MTS) will perform
high-speed logic design, RTL coding, logic verification, synthesis, and timing
analysis for a large, complex, high-speed ASIC, and work closely with engineers
involved in the physical design process. Synthesis will be performed using
Synopsys; timing tools used include Synopsys, Motive, and Perl. Logic design is
performed using Verilog.

This position requires an MS or PhD in Electrical Engineering, or equivalent,
plus 7 or more years experience in high-speed ASIC design. The successful
candidate will have a very good understanding of multiprocessor architecture,
cache coherency, Verilog/VHDL, Synopsys, and timing tools (Motive, Perl).
Knowledge in the area of I/O and Networking architectures is a plus.


415-933-4392, or call Susan Raskin at 415-933-4392. Silicon Graphics is an
equal opportunity employer. Principals only, please.

--
Susan Raskin                                    direct dial: 415-933-4523
ASD/NSD Staffing                                fax:         415-933-4392

2011 North Shoreline Boulevard                  web:   http://www.*-*-*.com/
MS 7U-553
Mountain View, CA  94043-1389



Tue, 10 Nov 1998 03:00:00 GMT  
 
 [ 1 post ] 

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