Truely Random 
Author Message
 Truely Random

Greetings:

        I am writing tests for a verification of a chip
        and want to randomize tasks. What I do is:

        yrand = {$dist_t(xrand,10000000)} % 5;
        case (yrand)
            32'h0 : task0;
            32'h1 : task1;
            32'h2 : task2;
            32'h3 : task3;
            32'h4 : task4;
            default: default_task;

        However each time I run the test the same sequence
        of tasks are run. I have tried $random and
        several of the other Verilog included random
        number generators, but get the same sequence.
        What am I doing wrong?

        Thanks for any help in advance

                Tom



Tue, 23 Oct 2001 03:00:00 GMT  
 Truely Random
What is xrand? For the $dist_t function here, xrand is being taken as a
"seed"; and, such random (actually, pseudo-random functions) will always
return the same value given the same seed.

If your xrand does not change between diff. runs; the o/p of $dist_t is
going to remain the same for diff. runs.

Thanks,
sanjay

Quote:

> Greetings:

>         I am writing tests for a verification of a chip
>         and want to randomize tasks. What I do is:

>         yrand = {$dist_t(xrand,10000000)} % 5;
>         case (yrand)
>             32'h0 : task0;
>             32'h1 : task1;
>             32'h2 : task2;
>             32'h3 : task3;
>             32'h4 : task4;
>             default: default_task;

>         However each time I run the test the same sequence
>         of tasks are run. I have tried $random and
>         several of the other Verilog included random
>         number generators, but get the same sequence.
>         What am I doing wrong?

>         Thanks for any help in advance

>                 Tom



Tue, 23 Oct 2001 03:00:00 GMT  
 Truely Random

Quote:

> Greetings:

>         I am writing tests for a verification of a chip
>         and want to randomize tasks. What I do is:

>         yrand = {$dist_t(xrand,10000000)} % 5;
>         case (yrand)
>             32'h0 : task0;
>             32'h1 : task1;
>             32'h2 : task2;
>             32'h3 : task3;
>             32'h4 : task4;
>             default: default_task;

>         However each time I run the test the same sequence
>         of tasks are run. I have tried $random and
>         several of the other Verilog included random
>         number generators, but get the same sequence.
>         What am I doing wrong?

>         Thanks for any help in advance

>                 Tom

Tom,

  You're not doing anything wrong. The random number generators are
supposed to generate
the same psuedorandom sequence every time you run IF you use the same
seed (in your case
that would be the variable xrand). A common way to randomize this is to
make the seed something
like the time of day. You'll need to write a PLI function in order to
obtain this. Also, I suggest that
you provide the capability of (1) displaying/logging the seed so you can
recreate the same sequence
of events should you encounter something you need to debug and
(2) explicitely setting the seed
(again for debug purposes).

  Have fun!

  --Bob

--
Bob Beckwith
To reply, remove NOSPAM. from the email address above.



Tue, 23 Oct 2001 03:00:00 GMT  
 Truely Random


Quote:
> Greetings:

> I am writing tests for a verification of a chip
> and want to randomize tasks. What I do is:

>         yrand = {$dist_t(xrand,10000000)} % 5;
>         case (yrand)
>             32'h0 : task0;
>             32'h1 : task1;
>             32'h2 : task2;
>             32'h3 : task3;
>             32'h4 : task4;
>             default: default_task;

> However each time I run the test the same sequence
> of tasks are run. I have tried $random and
> several of the other Verilog included random
> number generators, but get the same sequence.
> What am I doing wrong?

> Thanks for any help in advance

> Tom

You actually want the same sequence in case you discover
a bug, fix it and then rerun to make sure its fixed.

I typically will use a perl script to generate a random seed and
then "feed" the number thru the pli

#!/usr/bin/perl -w

$random_seed = int (rand(0x20));
system("verilog +pli_plusarg_random=$random_seed .......");

just another idea

ramon



Wed, 24 Oct 2001 03:00:00 GMT  
 Truely Random


Quote:
> Greetings:

>    I am writing tests for a verification of a chip
>    and want to randomize tasks. What I do is:

>         yrand = {$dist_t(xrand,10000000)} % 5;
>         case (yrand)
>             32'h0 : task0;
>             32'h1 : task1;
>             32'h2 : task2;
>             32'h3 : task3;
>             32'h4 : task4;
>             default: default_task;

>    However each time I run the test the same sequence
>    of tasks are run. I have tried $random and
>    several of the other Verilog included random
>    number generators, but get the same sequence.
>    What am I doing wrong?

>    Thanks for any help in advance

>            Tom

Tom,
I resend this since for some reason I don't think it was transmitted OK.
We, in Orckit have developped some random functions that will
necessarily answer your question since it is based on the Time of Day.
1.
$tod_srand(); may be used to generate a new seed based on the Time of
Day, so each time you run your simulation, you will get a new sequence.
You may preserve the seed by:
seed = $tod_srand();
2.
You may set a new, predefined seed by
$srand(seed);
3.
You may generate a sequence of random numbers by:
random_number = $rand();

Here is the short PLI source code:

#include "vcsuser.h" /* Base Verilog PLI definitions */
#include <sys/time.h>
#define RETURNV 0 /* Return value */
#define ARG1 1 /* First argument */
/****************************************************************/
/* Calltf routine for tod_srand function */
tod_srand_call() {
 struct timeval tp;
 void *vp;
 gettimeofday(&tp, vp );
 tf_putp(RETURNV, srand(tp.tv_sec));
 }
/****************************************************************/
/* Calltf routine for srand function */
srand_call() { srand(tf_getp(ARG1)); }

/****************************************************************/
/* Calltf routine for rand function */
rand_call() { tf_putp (RETURNV, rand()); }

The PLI table is:
$srand                   call=srand_call
$tod_srand               call=tod_srand_call size=32
$rand                    call=rand_call size=32

The verilog code may look like this:

module test;
integer i, rand, random_number;
initial
 begin
  seed = tod_srand(); // Set a unique, new seed, and save it
  for (i = 0; i < 10; i = i + 1)
   $display("%d", $rand());
 // Generate the above sequence again, in the same run
  $srand(seed);
  for ( i = 0; i < 10; i = i+1)
   $display("%d", $rand());
 end // initial

Hope it helps,
  Andi Carmon

--== Sent via Deja.com http://www.deja.com/ ==--
---Share what you know. Learn what you don't.---



Sat, 03 Nov 2001 03:00:00 GMT  
 
 [ 6 post ] 

 Relevant Pages 

1. Try This. It Truely Works

2. Try This. It Truely Works

3. random rant on random files

4. A truly random $random??

5. ? generating random uniform and binomial random deviates for BIG integers

6. Unit tests and random.Random()

7. Random number not random?

8. random behavior in random module?

9. Random Number Generator to produce SAME random number from 12:00am-11:59pm

10. Opening random line from file with random.shuffle()

11. Random Value

12. J random-number generator: what is used?

 

 
Powered by phpBB® Forum Software