Author Message

"Write your HDL test benches in Python!"

I am happy to announce the release of MyHDL 0.2, a python package for
using Python as a hardware description & verification language.

You can find it at http://www.*-*-*.com/

MyHDL 0.2

MyHDL is a Python package for using Python as a hardware description
language. Popular hardware description languages, like Verilog and
VHDL, are compiled languages. Python with MyHDL can be viewed as a
"scripting language" counterpart of such languages. However, Python is
more accurately described as a very high level language (VHLL). MyHDL
users have access to the amazing power and elegance of Python for
their modeling work.

The key idea behind MyHDL is to use Python generators to model the
concurrency required in hardware descriptions. As generators are a
recent Python feature, MyHDL requires Python 2.2.2 or higher.

MyHDL can be used to experiment with high level modeling, and with
verification techniques such as unit testing. The most important
practical application however, is to use it as a hardware verification
language by co-simulation with Verilog and VHDL.

The present release, MyHDL 0.2, enables MyHDL for co-simulation. The
MyHDL side is designed to work with any simulator that has a PLI. For
each simulator, an appropriate PLI module in C needs to be
provided. The release contains such a module for the Icarus Verilog

Jan Decaluwe - Resources bvba
Losbergenlaan 16, B-3010 Leuven, Belgium


Fri, 04 Nov 2005 16:27:27 GMT  
 [ 1 post ] 

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