ANN: Confluence -> Python for Hardware Verification 
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 ANN: Confluence -> Python for Hardware Verification

Over the weekend we released Confluence 0.4.6: the first
version to included the new python model generator.

Confluence is a functional programming language for hardware
and logic design.  Though its syntax is much simpler than
either Verilog or VHDL, it's semantics enables a level of
design flexibility beyond the reach of either HDL.

Til now, Confluence compiled into Verilog and VHDL for
logic synthesis and cycle-accurate C for high-speed simulation
and hardware-software co-development.

With the addition of the Python model generator, hardware
designers can now use the high-level constructs of our
favorite language (Python!) to perform functional verification.

We were very surprised by Python's simulation performance;
Python simulation of our benchmarks was right on par with
HDL event-based simulators.  Not bad for a "scripting" language!

For more info on Confluence:

  http://www.*-*-*.com/

To see Confluence output, including generated Python models
visit any of the Confluence projects at:

  http://www.*-*-*.com/

Regards,
Tom

--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790

http://www.*-*-*.com/



Sat, 19 Nov 2005 07:06:35 GMT  
 
 [ 1 post ] 

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