How do I change pulse width and delay on the fly? 
Author Message
 How do I change pulse width and delay on the fly?

I found a Pulse Width Modulator example which allows you to change the
frequency of a TTL pulse train on a counter without reconfiguring the
board (on the fly).  But, I would like to be able to change the pulse
width and pulse delay of a signal on the fly.  I am using a PCI-6601
device.

Any help would be greatly appreciated!



Tue, 28 Sep 2004 07:17:46 GMT  
 How do I change pulse width and delay on the fly?
Please take a look at this example.

It changes the Pulse Specs 1 and 2 inside the while loop. This exactly
can be adjusted to take care of the pulse width and delay on the fly.

<a href =
http://ae.natinst.com/devzone/explprog.nsf/41ee12ddba6c766a8625684700...>Pulse
Width on the fly</a>

Let me know if you any questions.

Sincerely,
Sastry V.
Applications Engineer
National Instruments.



Tue, 28 Sep 2004 23:35:36 GMT  
 How do I change pulse width and delay on the fly?
Thank you for your reply, but I am unable to view the link.  I get a
"Page can not be displayed" error.  Could you check the link for me?
I'm anxious to see the example and find a solution for my project!

Thank you.



Wed, 29 Sep 2004 00:11:34 GMT  
 How do I change pulse width and delay on the fly?
Thank you, I got the attachment.  This is the example that I already
have.  This example allows you to change frequency and duty cycle on
the fly, but what changes would I need to make to be able to change
pulse delay and pulse width on the fly?

If you could help or at least point me in the right direction, I would
appreciate it.



Wed, 29 Sep 2004 05:32:01 GMT  
 How do I change pulse width and delay on the fly?
Changing the duty cycle necessarily means changing the pule delay and
width. right?? If you take a look at the block diagram, Pulse Specs 1
and Pulse Spec2 are being changed on the fly. The no. of counts of
Pulse Specs 1 sets the Delay and the no. of counts of pulse specs 2
sets the width. So now you can edit it to get what you want.

once again , 50% duty cycle => equal pulse width and delay.

70% duty cycle is 0.7 width and 0.3 delay.

Am I right??

Sincerely,
Sastry V
Applications Engineer
National Instruments



Wed, 29 Sep 2004 05:55:02 GMT  
 
 [ 5 post ] 

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